參數(shù)資料
型號: 74LCX16240MTDX
廠商: Fairchild Semiconductor
文件頁數(shù): 1/8頁
文件大小: 0K
描述: IC INVERTER DUAL 8-INPUT 48TSSOP
標(biāo)準(zhǔn)包裝: 1,000
系列: 74LCX
邏輯類型: 逆變器,緩沖器
電路數(shù): 4
輸入數(shù): 4
特點: 三態(tài)
電源電壓: 2 V ~ 3.6 V
電流 - 靜態(tài)(最大值): 20µA
輸出電流高,低: 24mA,24mA
邏輯電平 - 低: 0.7 V ~ 0.8 V
邏輯電平 - 高: 1.7 V ~ 2 V
額定電壓和最大 CL 時的最大傳播延遲: 4.5ns @ 3.3V,50pF
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 48-TSSOP
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
包裝: 帶卷 (TR)
2005 Fairchild Semiconductor Corporation
DS011999
www.fairchildsemi.com
February 1994
Revised May 2005
7
4LCX16240
Low
V
o
lt
ag
e
16-
Bit
Inver
ti
ng
Buf
fer
/Li
ne
D
rive
rw
ith
5V
T
o
le
ra
nt
Input
s
and
Output
s
74LCX16240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 5V Tolerant Inputs and Outputs
General Description
The LCX16240 contains sixteen inverting buffers with
3-STATE outputs designed to be employed as a memory
and address driver, clock driver, or bus-oriented transmit-
ter/receiver. The device is nibble controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The LCX16240 is designed for low voltage (2.5V or 3.3V)
VCC applications with capacity of interfacing to a 5V signal
environment.
The LCX16240 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs
s 2.3V to 3.6V VCC specifications provided
s 4.5 ns tPD max (VCC 3.3V), 20 PA ICC max
s Power down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s
r24 mA output drive (VCC 3.0V)
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model
! 2000V
Machine model
! 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbol
Pin Descriptions
GTO
is a trademark of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
74LCX16240MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LCX16240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OEn
Output Enable Inputs (Active LOW)
I0–I15
Inputs
O0–O15
Outputs
s Implements proprietary noise/EMI reduction circuitry
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