參數(shù)資料
型號(hào): 74LCX16374TTR
廠商: 意法半導(dǎo)體
英文描述: LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS
中文描述: 低電壓CMOS 16位D型觸發(fā)器(三態(tài)容限為5V輸入和輸出)
文件頁(yè)數(shù): 5/10頁(yè)
文件大小: 193K
代理商: 74LCX16374TTR
74LCX16374
5/10
AC ELECTRICAL CHARACTERISTICS
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the samedevice switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
1) C
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/16 (per
circuit)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
R
L
(
)
t
s
=
t
r
(ns)
-40 to 85 °C
-55 to 125 °C
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time
2.7
50
500
2.5
1.5
1.5
1.5
6.5
6.2
6.3
1.5
1.5
1.5
6.5
6.2
6.3
ns
3.0 to 3.6
2.7
t
PZL
t
PZH
Output Enable Time
to HIGH and LOW
level
Output Disable Time
fromHIGHandLOW
level
Set-Up Time, HIGH
or LOW level
(Dn to CK)
Hold Time, HIGH or
LOW level
(Dn to CK)
CK Pulse Width,
HIGH or LOW
50
500
2.5
ns
3.0 to 3.6
1.5
6.1
1.5
6.1
t
PLZ
t
PHZ
2.7
50
500
2.5
1.5
6.2
1.5
6.2
ns
3.0 to 3.6
1.5
6.0
1.5
6.0
t
S
2.7
50
500
2.5
2.5
2.5
ns
3.0 to 3.6
2.5
2.5
t
h
2.7
50
500
2.5
1.5
1.5
ns
3.0 to 3.6
1.5
1.5
t
W
2.7
50
500
2.5
3.0
3.0
3.0
3.0
ns
3.0 to 3.6
f
MAX
Clock Pulse
Frequency
Output To Output
Skew Time (note1,
2)
3.0 to 3.6
50
500
2.5
170
150
MHz
t
OSLH
t
OSHL
3.0 to 3.6
50
500
2.5
1.0
1.0
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25 °C
Min.
Typ.
Max.
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
(note 1)
3.3
3.3
3.3
V
IN
= 0 to V
CC
V
IN
= 0 to V
CC
f
IN
= 10MHz
V
IN
= 0 or V
CC
7
8
20
pF
pF
pF
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