參數(shù)資料
型號: 74LCX574SJX
廠商: Fairchild Semiconductor
文件頁數(shù): 7/14頁
文件大?。?/td> 0K
描述: IC FLIP FLOP OCT D LV 20SOP
標準包裝: 2,000
系列: 74LCX
功能: 標準
類型: D 型總線
輸出類型: 三態(tài)非反相
元件數(shù): 1
每個元件的位元數(shù): 8
頻率 - 時鐘: 150MHz
延遲時間 - 傳輸: 8.5ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 24mA,24mA
電源電壓: 2 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LCX574 Rev. 1.6.1
2
74LCX574
Lo
w
V
olta
g
e
Octal
D-T
ype
Flip-Flop
with
5V
T
olerant
Inputs
and
Outputs
Connection Diagrams
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
Pad Assignments for DQFN
(Top View)
Pin Descriptions
Logic Symbol
Truth Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
Z
= High Impedance
= LOW-to-HIGH Transition
NC
= No Change
Functional Description
The LCX574 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the con-
tents of the eight flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
state. Operation of the OE input does not affect the load-
ing of the flip-flops.
Pin Names
Description
D0–D7
Data Inputs
CP
Clock Pulse Input
OE
3-STATE Output Enable Input
O0–O7
3-STATE Outputs
D1
D2
D3
D4
D5
D6
D7
GND
D0
O1
O2
O3
O4
O5
O6
O7
CP
O0
VCC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
D1
D2
D3
D4
D5
D6
D7
GND
D0
O1
O2
O3
O4
O5
O6
O7
CP
O0
VCC
120
2
3
4
5
6
7
8
9
10
11
19
18
17
16
15
14
13
12
OE
Inputs
Internal Outputs
Function
OE CP
D
Q
On
HH
LNCZ
Hold
HH
HNCZ
Hold
HL
HZ
Load
HH
LZ
Load
LL
HL
Data Available
LH
Data Available
LH
LNCNC
No Change in Data
LH
HNCNC
No Change in Data
D0 D1 D2 D3 D4 D5 D6 D7
O0
OE
CP
O1 O2 O3 O4 O5 O6 O7
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.
C
O0
CP
OE
O1
O2
O3
O4
O5
O6
O7
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
(Bottom View)
DAP
No Connect
Note: DAP (Die Attach Pad)
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