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參數(shù)資料
| 型號： | 74LS165 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 8-Bit Parallel In/Serial Output Shift Registers |
| 中文描述： | 8位并行/串行輸出移位寄存器 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 73K |
| 代理商： | 74LS165 |
2000 Fairchild Semiconductor Corporation
DS006399
www.fairchildsemi.com
August 1986
Revised March 2000
D
DM74LS165
8-Bit Parallel In/Serial Output Shift Registers
General Description
This device is an 8-bit serial shift register which shifts data
in the direction of Q
A
toward Q
H
when clocked. Parallel-in
access is made available by eight individual direct data
inputs, which are enabled by a low level at the shift/load
input. These registers also feature gated clock inputs and
complementary outputs from the eighth bit.
Clocking is accomplished through a 2-input NOR gate, per-
mitting one input to be used as a clock-inhibit function.
Holding either of the clock inputs HIGH inhibits clocking,
and holding either clock input LOW with the load input
HIGH enables the other clock input. The clock-inhibit input
should be changed to the high level only while the clock
input is HIGH. Parallel loading is inhibited as long as the
load input is HIGH. Data at the parallel inputs are loaded
directly into the register on a HIGH-to-LOW transition of the
shift/load input, regardless of the logic levels on the clock,
clock inhibit, or serial inputs.
Features
I
Complementary outputs
I
Direct overriding (data) inputs
I
Gated clock inputs
I
Parallel-to-serial data conversion
I
Typical frequency 35 MHz
I
Typical power dissipation 105 mW
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
H
=
HIGH Level (steady state)
L
=
LOW Level (steady state)
X
=
Don't Care (any input, including transitions)
↑
=
Transition from LOW-to-HIGH level
a...h
=
The level of steady-state input at inputs A through H, respectively.
Q
A0
, Q
B0
, Q
H0
=
The level of Q
A
, Q
B
, or Q
H
, respectively, before the
indicated steady-state input conditions were established.
Q
An
, Q
Gn
=
The level of Q
A
or Q
G
, respectively, before the most recent
↑
transition of the clock.
Order Number
DM74LS165M
DM74LS165WM
DM74LS165N
Package Number
M16A
M16B
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Internal
Shift/ Clock Clock Serial Parallel Outputs Output
Load Inhibit
L
X
X
X
H
L
L
X
H
L
↑
H
H
L
↑
L
H
H
X
X
A...H
a...h
X
X
X
X
Q
A
a
Q
A0
Q
B0
H
L
Q
A0
Q
B0
Q
B
b
Q
H
h
Q
H0
Q
Gn
Q
Gn
Q
H0
Q
An
Q
An
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LS165DC | 制造商:Texas Instruments 功能描述: |
| 74LS165PC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| 74LS165SC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| 74LS166 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-BIT SHIFT REGISTERS |
| 74LS166N | 制造商:Motorola 功能描述:SN74LS166N 制造商:National Semiconductor 功能描述:74LS166N |
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