參數(shù)資料
型號: 74LV107PW
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: CLP SINE
中文描述: LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝: 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP1-14
文件頁數(shù): 6/12頁
文件大小: 121K
代理商: 74LV107PW
Philips Semiconductors
Product specification
74LV107
Dual JK flip-flop with reset; negative-edge trigger
1998 Apr 20
6
AC CHARACTERISTICS (Continued)
GND = 0V; t
r
= t
f
2.5ns; C
L
= 50pF; R
L
= 1K
SYMBOL
PARAMETER
WAVEFORM
CONDITION
V
CC
(V)
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
2.0
2.7
3.0 to 3.6
4.5 to 5.5
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
2.0
2.7
3.0 to 3.6
4.5 to 5.5
–40 to +85
°
C
TYP
1
95
32
24
18
2
–40 to +125
°
C
MIN
UNIT
MIN
MAX
MAX
Propagation delay
nR to nQ, nQ
44
33
26
22
56
41
33
28
t
PHL
/t
PLH
Figures 1, 2
ns
34
25
20
15
34
25
20
15
14
10
8
2
41
30
24
18
41
30
24
t
W
Clock pulse width
HIGH or LOW
Figure 2
ns
14
10
8
2
t
W
Reset pulse width
LOW
Figure 2
ns
35
12
9
7
2
Removal time
nR to nCP
24
18
14
11
29
21
17
14
t
rem
Figure 2
ns
40
14
10
8
2
Set up time
Set-up time
nJ, nK to CP
26
19
15
12
31
23
18
15
t
su
Figure 1
ns
-10
–3
–2
–2
2
Hold time
nJ, nK to CP
5
5
5
5
14
19
24
30
5
5
5
5
12
16
20
24
t
h
Figure 1
ns
40
58
70
2
f
max
Maximum clock
pulse frequency
Figure 1
MHz
NOTES:
1. Unless otherwise stated, all typical values are measured at T
amb
= 25
°
C
2. Typical values are measured at V
CC
= 3.3 V.
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