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參數資料
| 型號： | 74LV10 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Triple 3-input NAND gate |
| 中文描述： | 三3輸入與非門 |
| 文件頁數： | 2/10頁 |
| 文件大?。?/td> | 113K |
| 代理商： | 74LV10 |
Philips Semiconductors
Product specification
74LV10
Triple 3-input NAND gate
2
1998 Apr 20
853–1919 19256
FEATURES
Optimized for Low Voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
T
amb
= 25
°
C.
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V,
T
amb
= 25
°
C.
Output capability: standard
I
CC
category: SSI
DESCRIPTION
The 74LV10 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT10.
The 74LV10 provides the 3-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
SYMBOL
2.5 ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
nA, nB, nC to nY
C
L
= 15 pF;
V
CC
= 3.3 V
9
ns
C
I
C
PD
Input capacitance
3.5
pF
Power dissipation capacitance per gate
See Notes 1 and 2
12
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
×
V
CC2
×
f
i
(C
L
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
V
CC2
f
o
) where:
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
14-Pin Plastic DIL
–40
°
C to +125
°
C
74LV10 N
74LV10 N
SOT27-1
14-Pin Plastic SO
–40
°
C to +125
°
C
74LV10 D
74LV10 D
SOT108-1
14-Pin Plastic SSOP Type II
–40
°
C to +125
°
C
74LV10 DB
74LV10 DB
SOT337-1
14-Pin Plastic TSSOP Type I
–40
°
C to +125
°
C
74LV10 PW
74LV10PW DH
SOT402-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1, 3, 9
1A – 3A
Data inputs
2, 4, 10
1B – 3B
Data inputs
7
GND
Ground (0 V)
12, 6, 8
1Y – 3Y
Data outputs
13, 5, 11
1C – 3C
Data inputs
14
V
CC
Positive supply voltage
FUNCTION TABLE
INPUTS
OUTPUTS
nA
nB
nC
nY
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
L
NOTES:
H = HIGH voltage level
L = LOW voltage level
相關PDF資料 |
PDF描述 |
|---|---|
| 74LV11 | Triple 3-input AND gate |
| 74LV11D | Triple 3-input AND gate |
| 74LV11DB | Triple 3-input AND gate |
| 74LV11N | Triple 3-input AND gate |
| 74LV11PW | Triple 3-input AND gate |
相關代理商/技術參數 |
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| 74LV107 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual JK flip-flop with reset; negative-edge trigger |
| 74LV107D | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual JK flip-flop with reset; negative-edge trigger |
| 74LV107DB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual JK flip-flop with reset; negative-edge trigger |
| 74LV107DB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
| 74LV107D-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
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