參數(shù)資料
型號: 74LV377PWDH
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: Octal D-type flip-flop with data enable; positive edge-trigger
中文描述: LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
封裝: PLASTIC, TSSOP-20
文件頁數(shù): 2/12頁
文件大?。?/td> 114K
代理商: 74LV377PWDH
Philips Semiconductors
Product specification
74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
2
1998 Jun 10
853–1935 19545
FEATURES
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
Typical V
OLP
(output ground bounce)
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot)
T
amb
= 25
°
C
Ideal for addressable register applications
Data enable for address and data synchronization applications
Eight positive-edge triggered D-type flip-flops
Output capability: standard
I
CC
category: MSI
0.8V @ V
CC
= 3.3V,
2V @ V
CC
= 3.3V,
DESCRIPTION
The 74LV377 is a low–voltage CMOS device and is pin and function
compatible with 74HC/HCT377.
The 74LV377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. A common clock (CP) input loads
all flip-flops simultaneously when the data enable (E) is LOW. The
state of each D input, one set-up time before the LOW-to-HIGH
clock transition, is transferred to the corresponding output (Q
n
) of
the flip-flop. The E input must be stable only one set-up time prior to
the LOW-to-HIGH transition for predictable operation.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
= t
f
SYMBOL
2.5 ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
CP to Q
n
Maximum clock frequency
C
L
= 15pF
V
CC
= 3.3V
3 3V
13
ns
f
max
C
I
C
PD
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
V
CC2
f
i
(C
L
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
77
MHz
Input capacitance
3.5
pF
Power dissipation capacitance per flip-flop
Notes 1 and 2
20
pF
V
CC2
f
o
) where:
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic DIL
74LV377 N
74LV377 N
SOT146-1
20-Pin Plastic SO
74LV377 D
74LV377 D
SOT163-1
20-Pin Plastic SSOP Type II
74LV377 DB
74LV377 DB
SOT339-1
20-Pin Plastic TSSOP Type I
74LV377 PW
74LV377PW DH
SOT360-1
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
E
Data enable input (active-LOW)
2, 5, 6, 9, 12,
15, 16, 19
3, 4, 7, 8, 13,
14, 17, 18
10
Q
0
to Q
7
flip-flop outputs
D
0
to D
7
Data inputs
GND
Ground (0V)
11
CP
Clock input
(LOW-to-HIGH, edge-triggered)
Positive supply voltage
20
V
CC
FUNCTION TABLE
OPERATING MODES
INPUTS
OUTPUTS
CP
X
E
l
D
n
h
Q
n
H
Load ‘‘1’’
Load ‘‘0’’
l
l
L
Hold (do nothing)
h
H
X
X
No change
No change
H
h
=
=
HIGH voltage level
HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
LOW voltage level
LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
LOW–to–HIGH CP transition
Don’t care
L
l
=
=
X
=
=
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