參數(shù)資料
型號: 74LVC161PW,112
廠商: NXP Semiconductors
文件頁數(shù): 4/22頁
文件大?。?/td> 0K
描述: IC SYNC 4BIT BIN COUNTER 16TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標準包裝: 96
系列: 74LVC
邏輯類型: 二進制計數(shù)器
方向:
元件數(shù): 1
每個元件的位元數(shù): 4
復(fù)位: 異步
計時: 同步
計數(shù)速率: 150MHz
觸發(fā)器類型: 正邊沿
電源電壓: 1.2 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
其它名稱: 74LVC161PW
74LVC161PW-ND
935210530112
74LVC161
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 30 September 2013
12 of 22
NXP Semiconductors
74LVC161
Presettable synchronous 4-bit binary counter; asynchronous reset
11. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9.
Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, and maximum frequency
mna911
CP input
Qn, TC output
tPHL
tPLH
tW
1/fmax
VM
VOH
VI
GND
VOL
VM
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. Input (CET) to output (TC) propagation delays
mna912
tPHL
tPLH
VM
TC output
CET input
GND
VI
VOH
VOL
Fig 11. Master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays, and the master
reset to clock (CP) removal times
mna913
MR input
CP input
Qn, TC output
tPHL
tW
trec
VM
VOH
VI
GND
VOL
VM
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