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參數(shù)資料
| 型號： | 74LVC16374ADGG,118 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 16BIT EDGE TRIG D FF 48TSSOP |
| 產(chǎn)品培訓模塊： | Logic Packages |
| 標準包裝： | 2,000 |
| 系列： | 74LVC |
| 功能： | 標準 |
| 類型： | D 型總線 |
| 輸出類型： | 三態(tài)非反相 |
| 元件數(shù)： | 2 |
| 每個元件的位元數(shù)： | 8 |
| 頻率 - 時鐘： | 150MHz |
| 延遲時間 - 傳輸： | 7ns |
| 觸發(fā)器類型： | 正邊沿 |
| 輸出電流高，低： | 24mA，24mA |
| 電源電壓： | 1.65 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 包裝： | 帶卷 (TR) |
1.
General description
The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring
separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state
outputs for bus-oriented applications. It consists of two sections of eight positive
edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE) are provided for
each octal.
The flip-flops store the state of their individual D-inputs that meet the set-up and hold time
requirements on the LOW-to-HIGH clock (CP) transition.
When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin
nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE
does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed 3.3 V and
5 V applications.
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused
inputs.
2.
Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pinout architecture
Low inductance multiple supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16374A only)
High-impedance outputs when VCC = 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C to +85 C and 40 C to +125 C
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
Rev. 11 — 16 January 2013
Product data sheet
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| 74LVC16374ADGG-Q1J | 制造商:NXP Semiconductors 功能描述:74LVC16374ADGG-Q100/TSSOP48/RE 制造商:NXP Semiconductors 功能描述:Flip Flop D-Type Bus Interface Pos-Edge 3-ST 2-Element 48-Pin TSSOP T/R 制造商:NXP Semiconductors 功能描述:74LVC16374ADGG-Q100/TSSOP48/RE - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC FLIP FLOP D-TYPE DUAL 48TSSOP |
| 74LVC16374ADGGRG4 | 功能描述:觸發(fā)器 16-Bit Edg-Trig D-Ty F-F W/3-State Otpt RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74LVC16374ADG-T | 功能描述:觸發(fā)器 3.3V 16-BIT POS D-TYPE 3-S RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74LVC16374ADGVRE4 | 功能描述:觸發(fā)器 16-Bit Edg-Trig D-Ty F-F W/3-State Otpt RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74LVC16374ADGVRG4 | 功能描述:觸發(fā)器 16B Edge-Triggered D-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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