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參數(shù)資料
| 型號： | 74LVC1G58GW,125 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONFIG MULTI-FUNC GATE SC-88 |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 74LVC |
| 邏輯類型： | 可配置多功能 |
| 電路數(shù)： | 1 |
| 輸入數(shù)： | 3 |
| 施密特觸發(fā)器輸入： | 是 |
| 輸出類型： | 單端 |
| 輸出電流高，低： | 32mA，32mA |
| 電源電壓： | 1.65 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-TSSOP，SC-88，SOT-363 |
| 供應(yīng)商設(shè)備封裝： | 6-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 840 (CN2011-ZH PDF) |
| 其它名稱： | 568-4837-6 |
2009-2012 Microchip Technology Inc.
Preliminary
DS41393B-page 21
5.0
SPI COMMUNICATIONS
SPI operates in Slave mode with an Idle low SCK and
data transmitted on the SCK falling edge.
5.1
SPI Hardware Interface
A summary of the hardware interface pins is shown
below in Table 5-1.
SCK Pin
The AR1021 controller’s SCL/SCK/TX pin
receives Serial Clock (SCK), controlled by the
host.
The Idle state of the SCK should be low.
Data is transmitted on the falling edge of SCK.
SDI Pin
The AR1021 controller’s SDI/SDA/RX pin reads
Serial Data Input (SDI), sent by the host.
SDO Pin
The AR1021 controller’s SDO pin presents Serial
Data Output (SDO) to the host.
SIQ Pin
The AR1021 controller’s SIQ pin provides an
optional interrupt output from the controller to the
host.
The SIQ pin is asserted high when the controller
has data available (a touch report or a command
response) for the host.
The SIQ pin is deasserted after the host clocks
out the first byte of the data packet.
SS Pin
The AR1021 controller’s SS pin provides optional
“slave select” functionality.
In the ‘inactive’ state, the controller’s SDO pin presents
a high-impedance in order to prevent bus contention
with another device on the SPI bus.
TABLE 5-1:
SPI HARDWARE INTERFACE
AR1021 Pin
Description
M1
Connect to VDD to select SPI communications
SDI
Serial data sent from master
SCK
Serial clock to master
SDO
Serial data to master SPI
SIQ
Interrupt output to master (optional)
SS
Slave Select (optional)
Note:
The AR1000 Development kit PICkit
Serial Pin 1 is designated for the SIQ
interrupt pin after the firmware updated is
executed for the PICkit.
SS Pin Level
AR1021 Select
VSS
Active
VDD
Inactive
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