參數(shù)資料
型號(hào): 74LVC1G80GN,132
廠商: NXP Semiconductors
文件頁數(shù): 1/21頁
文件大?。?/td> 0K
描述: IC FLIP FLOP SGL D POS 6XSON
特色產(chǎn)品: MicroPak?
標(biāo)準(zhǔn)包裝: 5,000
系列: 74LVC
功能: 標(biāo)準(zhǔn)
類型: D 型
輸出類型: 反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 1
頻率 - 時(shí)鐘: 400MHz
延遲時(shí)間 - 傳輸: 1.8ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 32mA,32mA
電源電壓: 1.65 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 6-XFDFN
包裝: 帶卷 (TR)
其它名稱: 74LVC1G80GN132
1.
General description
The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop.
Information on the data input is transferred to the Q output on the LOW-to-HIGH transition
of the clock pulse. The input pin D must be stable one set-up time prior to the
LOW-to-HIGH clock transition for predictable operation.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2.
Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
24 mA output drive (V
CC =3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from
40 Cto+85 C and 40 Cto+125 C.
74LVC1G80
Single D-type flip-flop; positive-edge trigger
Rev. 12 — 2 July 2012
Product data sheet
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