參數(shù)資料
型號: 74LVC273
廠商: NXP Semiconductors N.V.
英文描述: Quadruple 2-Input Positive-OR Gates 14-SOIC -40 to 85
中文描述: 八路D型觸發(fā)器的復位觸發(fā)器,積極邊緣觸發(fā)
文件頁數(shù): 5/10頁
文件大小: 95K
代理商: 74LVC273
Philips Semiconductors
Product specification
74LVC273
Octal D-type flip-flop with reset; positive-edge trigger
1998 May 20
5
AC CHARACTERISTICS
GND = 0V; t
R
= t
F
= 2.5ns; C
L
= 50pF; R
L
= 500
; T
amb
= –40
°
C to +85
°
C.
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V
±
0.3V
MIN
TYP
1
V
CC
= 2.7V
TYP
UNIT
MAX
MIN
MAX
t
PHL
t
PLH
Propagation delay
CP to Qn
Propagation delay
MR to Qn
Clock pulse width
HIGH or LOW
Master reset pulse
width LOW
Removal time
MR to CP
Set-up time
D
n
to CP
Hold time
D
n
to CP
Maximum clock
pulse frequency
1
6.0
10.2
6.6
11.2
ns
t
PHL
2
6.3
11.0
7.4
12.0
ns
t
W
1
4
1.2
5
1.8
ns
t
W
2
4
1.2
5
1.7
ns
t
rem
2
2
–1.0
3
–1.0
ns
t
su
3
2
0.7
3
1.0
ns
t
h
3
0
–0.6
0
–0.9
ns
f
max
1
125
100
MHz
NOTE:
1. These typical values are at V
CC
= 3.3V and T
amb
= 25
°
C.
AC WAVEFORMS
V
M
= 1.5V at V
V
M
= 0.5 V
CC
at V
CC
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
2.7V.
2.7V.
V
M
V
M
1/f
MAX
t
w
t
PHL
t
PLH
CP INPUT
Qn OUTPUT
SW00078
GND
V
OH
V
OL
V
I
Waveform 1. Clock (CP) to output (Q
n
) propagation delays, the
clock pulse width and the maximum clock pulse frequency
V
M
MR INPUT
Qn OUTPUT
t
w
t
PHL
t
rem
CP INPUT
SY00053
V
CC
GND
V
CC
GND
V
OH
V
OL
V
M
V
M
V
M
Waveform 2. Master reset (MR) pulse width, the master reset to
output (Q
n
) propagation delays and the master reset to clock
(CP) removal time
V
M
SW00079
V
I
GND
éééé
éééé
éééé
ééééééé
ééééééé
ééééééé
V
M
Dn
INPUT
GND
V
M
V
OH
Qn
OUTPUT
V
OL
CP
INPUT
t
su
h
t
su
h
NOTE:
The shaded areas indicate when the input is permitted to change
for predictable output performance.
Waveform 3. Data set-up and hold times for the data input (D
n
)
相關(guān)PDF資料
PDF描述
74LVC273PWDH Quadruple 2-Input Positive-OR Gates 14-SOIC -40 to 85
74LVC27 Quadruple 2-Input Positive-OR Gates 14-SSOP -40 to 85
74LVC27PWDH Quadruple 2-Input Positive-OR Gates 14-SOIC -40 to 85
74LVC2952APWDH Octal registered tranceiver with 5-volt tolerant inputs/ouputs 3-State
74LVC2952A Quadruple 2-Input Positive-OR Gates 14-SOIC -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
74LVC2734AE4Q 制造商:Integrated Device Technology Inc 功能描述:
74LVC273AE4Q 制造商:Integrated Device Technology Inc 功能描述:
74LVC273APGG 制造商:Integrated Device Technology Inc 功能描述:DUAL NEG. FLIP FLOP 制造商:Integrated Device Technology Inc 功能描述:Flip Flop D-Type Bus Interface Pos-Edge 1-Element 20-Pin TSSOP Tube
74LVC273APGG8 制造商:Integrated Device Technology Inc 功能描述:Flip Flop D-Type Bus Interface Pos-Edge 1-Element 20-Pin TSSOP T/R 制造商:Integrated Device Technology Inc 功能描述:IC FLIP FLOP OCTAL D 20-TSSOP
74LVC273AQ20-13 功能描述:IC D-TYPE POS TRG SNGL 20QFN 制造商:diodes incorporated 系列:74LVC 包裝:剪切帶(CT) 零件狀態(tài):有效 功能:復位 類型:D 型 輸出類型:非反相 元件數(shù):1 每元件位數(shù):8 頻率 - 時鐘:230MHz 不同 V,最大 CL 時的最大傳播延遲:7.3ns @ 3.3V,50pF 觸發(fā)器類型:正邊沿 電流 - 輸出高,低:24mA,24mA 電壓 - 電源:1.65 V ~ 3.6 V 電流 - 靜態(tài):10μA 輸入電容:4pF 工作溫度:-40°C ~ 125°C(TA) 安裝類型:表面貼裝 封裝/外殼:20-VFQFN 裸露焊盤 標準包裝:1