參數(shù)資料
型號(hào): 74LVC543ABQ,118
廠商: NXP Semiconductors
文件頁(yè)數(shù): 15/20頁(yè)
文件大小: 0K
描述: IC REGISTERED TXRX 8BIT 24QFN
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 3,000
系列: 74LVC
邏輯類型: 寄存收發(fā)器,非反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
輸出電流高,低: 24mA,24mA
電源電壓: 1.2 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-DHVQFN(5.5x3.5)
包裝: 帶卷 (TR)
其它名稱: 74LVC543ABQ-T
74LVC543ABQ-T-ND
935275378118
74LVC543A_8
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 18 December 2012
4 of 20
NXP Semiconductors
74LVC543A
Octal D-type registered transceiver; 3-state
5.
Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration for SO24 and (T)SSOP24
Fig 5.
Pin configuration for DHVQFN24
74LVC543A
LEBA
VCC
OEBA
EBA
A0
B0
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
EAB
LEAB
GND
OEAB
001aaa341
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
001aaa340
74LVC543A
Transparent top view
11
14
10
15
9
16
8
17
7
18
6
19
5
20
4
21
3
22
2
23
12
13
1
24
terminal 1
index area
EBA
A0
OEBA
B0
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
EAB
LEAB
LEBA
V
CC
GND
OEAB
GND(1)
Table 2.
Pin description
Symbol
Pin
Description
LEBA
1
B to A latch enable input (active LOW)
LEAB
14
A to B latch enable input (active LOW)
OEBA
2
B to A output enable input (active LOW)
OEAB
13
A to B output enable input (active LOW)
EBA
23
B to A enable input (active LOW)
EAB
11
A to B enable input (active LOW)
A[0:7]
3, 4, 5, 6, 7, 8, 9, 10
A data input or output
B[0:7]
22, 21, 20, 19, 18, 17, 16, 15
B data output or input
GND
12
ground (0 V)
VCC
24
supply voltage
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