參數(shù)資料
型號(hào): 74LVC543APW,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 20/20頁(yè)
文件大?。?/td> 0K
描述: IC REGISTERED TXRX 8BIT 24TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 63
系列: 74LVC
邏輯類型: 寄存收發(fā)器,非反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
輸出電流高,低: 24mA,24mA
電源電壓: 1.2 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
其它名稱: 74LVC543APW
74LVC543APW-ND
935245870112
74LVC543A_8
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 18 December 2012
9 of 20
NXP Semiconductors
74LVC543A
Octal D-type registered transceiver; 3-state
[1]
Typical values are measured at Tamb =25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2]
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3]
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4]
CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD VCC2 fi N+ (CL VCC2 fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(C
L VCC
2
f
o) = sum of the outputs
11. AC waveforms
th
hold time
An, Bn to LEAB, LEBA, EAB, EBA;
VCC = 1.65 V to 1.95 V
4.0
-
4.0
-
ns
VCC = 2.3 V to 2.7 V
2.5
-
2.5
-
ns
VCC = 2.7 V
1.5
-
1.5
-
ns
VCC = 3.0 V to 3.6 V
1.5
0.6
-
1.5
-
ns
tsk(o)
output skew
time
VCC = 3.0 V to 3.6 V
-
1.0
-
1.5
ns
CPD
power
dissipation
capacitance
VI =GND to VCC
VCC = 1.65 V to 1.95 V
-
8.3
-
pF
VCC = 2.3 V to 2.7 V
-
11.9
-
pF
VCC = 3.0 V to 3.6 V
-
15.2
-
pF
Table 7.
Dynamic characteristics ...continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6.
Input (An and Bn) to output (Bn and An) propagation delays
mna751
An, Bn input
Bn, An output
tPHL
tPLH
GND
VI
VM
VOH
VOL
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