參數(shù)資料
型號: 74LVCH16244A
廠商: NXP Semiconductors N.V.
英文描述: 16-bit buffer/line driver;5V input/output tolerant (3-State)(5V輸入/輸出容限的16位緩沖器/線驅(qū)動器(三態(tài)))
中文描述: 16位緩沖器/線路驅(qū)動器,5V的輸入/輸出寬容(3態(tài))(5V的輸入/輸出容限的16位緩沖器/線驅(qū)動器(三態(tài)))
文件頁數(shù): 2/10頁
文件大?。?/td> 78K
代理商: 74LVCH16244A
Philips Semiconductors
Product specification
74LVC16244A/
74LVCH16244A
16-bit buffer/line driver; 5V input/output tolerant
(3-State)
2
1997 Oct 28
853-1994 18612
FEATURES
5 volt tolerant inputs/outputs for interfacing with 5V logic
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTE
TM
flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum
noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16244A only)
DESCRIPTION
The 74LVC(H)16244A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families. Inputs can be driven from either
3.3V or 5V devices. In 3-State operation, outputs can handle 5V.
These features allow the use of these devices in a mixed 3.3V/5V
environment.
The 74LVC(H)16244A is a 16-bit non-inverting buffer/line driver with
3-State outputs. The device can be used as four 4-bit buffers, two
8-bit buffers or one 16-bit buffer. The 3-State outputs are controlled
by the output enable inputs 1OE and 2OE. A HIGH on nOE causes
the outputs to assume a high impedance OFF-state. The device can
be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer.
The 74LVC(H)16244A is identical to the 74LVC16240A but has
non-inverting outputs.
The 74LVCH16244A bus hold data inputs eliminates the need for
external pull up resistors to hold unused inputs.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
1OE
1Y0
1Y1
GND
1Y2
1Y3
V
CC
2Y1
GND
2Y2
2Y3
3Y0
3Y1
GND
2Y0
3Y2
3Y3
V
CC
4Y0
4Y1
4A1
4A0
V
CC
3A3
3A2
GND
3A1
3A0
2A3
2A2
GND
2A1
2A0
V
CC
1A3
1A2
GND
1A1
1A0
2OE
21
22
23
24
25
26
27
28
GND
4Y2
4Y3
4OE
3OE
4A3
4A2
GND
SW00194
ORDERING INFORMATION
PACKAGES
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
OUTSIDE NORTH AMERICA
74LVC16244A DL
74LVC16244A DGG
74LVCH16244A DL
74LVCH16244A DGG
NORTH AMERICA
VC16244A DL
VC16244A DGG
VCH16244A DL
VCH16244A DGG
DWG NUMBER
SOT370-1
SOT362-1
SOT370-1
SOT362-1
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
2.5 ns
SYMBOL
Propagation delay
1An to 1Yn;
2An to 2Yn
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
C
L
= 50pF
V
CC
= 3.3V
3.0
ns
C
I
C
PD
Input capacitance
Power dissipation capacitance per buffer
5.0
25
pF
pF
V
I
= GND to V
CC1
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
相關(guān)PDF資料
PDF描述
74LVC16244 Quadruple 2-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs 16-SOIC -40 to 85
74LVC16245ADGG 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
74LVC16245ADL 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
74LVC16245AEV 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
74LVCH16245ADGG 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
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