參數(shù)資料
型號(hào): 74LVCH16374ADGG:11
廠商: NXP Semiconductors
文件頁(yè)數(shù): 20/20頁(yè)
文件大小: 0K
描述: IC 16BIT EDGE TRIG D FF 48TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 39
系列: 74LVCH
功能: 標(biāo)準(zhǔn)
類(lèi)型: D 型總線
輸出類(lèi)型: 三態(tài)非反相
元件數(shù): 2
每個(gè)元件的位元數(shù): 8
頻率 - 時(shí)鐘: 150MHz
延遲時(shí)間 - 傳輸: 7ns
觸發(fā)器類(lèi)型: 正邊沿
輸出電流高,低: 24mA,24mA
電源電壓: 1.2 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
包裝: 帶卷 (TR)
其它名稱: 935238510112
74LVC_LVCH16374A
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 11 — 16 January 2013
9 of 20
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
[1]
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25 C.
[2]
The bus hold circuit is switched off when VI >VCC allowing 5.5 V on the input pin.
[3]
Valid for data inputs (74LVCH16374A) only; control inputs do not have a bus hold circuit.
[4]
The specified sustaining current at the data inputs holds the input below the specified VI level.
[5]
The specified overdrive current at the data input forces the data input to the opposite logic input state.
10. Dynamic characteristics
IBHHO
bus hold
HIGH
overdrive
current
VCC = 1.95 V [3][5]
200
-
200
-
A
VCC = 2.7 V
300
-
300
-
A
VCC = 3.6 V
500
-
500
-
A
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
tpd
propagation
delay
nCP to nQn; see Figure 7
VCC = 1.2 V
-
14
-
ns
VCC = 1.65 V to 1.95 V
2.1
6.9
13.5
2.1
15.6
ns
VCC = 2.3 V to 2.7 V
1.5
3.7
6.7
1.5
7.7
ns
VCC = 2.7 V
1.5
3.4
6.0
1.5
7.5
ns
VCC = 3.0 V to 3.6 V
1.5
3.1
5.4
1.5
7.0
ns
ten
enable time
nOE to nQn; see Figure 9
VCC = 1.2 V
-
20
-
ns
VCC = 1.65 V to 1.95 V
1.5
5.9
13.1
1.5
15.1
ns
VCC = 2.3 V to 2.7 V
1.5
3.4
6.9
1.5
8.0
ns
VCC = 2.7 V
1.5
3.6
6.0
1.5
7.5
ns
VCC = 3.0 V to 3.6 V
1.0
2.7
5.2
1.0
6.5
ns
tdis
disable time
nOE to nQn; see Figure 7
VCC = 1.2 V
-
12
-
ns
VCC = 1.65 V to 1.95 V
2.8
4.6
9.1
2.8
10.5
ns
VCC = 2.3 V to 2.7 V
1.0
2.5
4.9
1.0
5.7
ns
VCC = 2.7 V
1.5
3.4
5.1
1.5
6.5
ns
VCC = 3.0 V to 3.6 V
1.5
3.1
4.9
1.5
6.5
ns
tW
pulse width
nCP HIGH; see Figure 7
VCC = 1.65 V to 1.95 V
5.0
-
5.0
-
ns
VCC = 2.3 V to 2.7 V
4.0
-
4.0
-
ns
VCC = 2.7 V
3.0
-
3.0
-
ns
VCC = 3.0 V to 3.6 V
3.0
1.5
-
3.0
-
ns
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