參數(shù)資料
型號(hào): 74LVQ541TTR
廠商: 意法半導(dǎo)體
英文描述: OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NO INVERTED)
中文描述: 八路總線緩沖器與三態(tài)輸出(編號(hào)順序排列):
文件頁(yè)數(shù): 1/12頁(yè)
文件大小: 268K
代理商: 74LVQ541TTR
1/12
July 2004
I
HIGH SPEED:
t
PD
=5.8 ns (TYP.) at V
CC
= 3.3 V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
CC
= 4
μ
A (MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.4V (TYP.) at V
CC
= 3.3V
75
TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 541
IMPROVED LATCH-UP IMMUNITY
I
I
I
I
I
I
I
I
I
I
DESCRIPTION
The 74LVQ541 is a low voltage CMOS OCTAL
BUS BUFFER with 3 STATE OUTPUTS NON
INVERTED fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
The 3-STATE control gate operates as two input
and such that if either G1 and G2 are high, all
eight outputs are in the high impedance state. In
order to enhance PC board layout, the 74AC541
offers a pinout having inputs and outputs on
opposite side of the package.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ541
OCTAL BUS BUFFER
WITH 3 STATE OUTPUTS (NON INVERTED)
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE
T & R
SOP
TSSOP
74LVQ541MTR
74LVQ541TTR
TSSOP
SOP
Rev. 2
相關(guān)PDF資料
PDF描述
74LVQ573 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING
74LVQ573M OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING
74LVQ573T OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING
74LVQ573QSC Low Voltage Octal Latch with 3-STATE Outputs
74LVQ573 Low Voltage Octal Latch with 3-STATE Outputs
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