參數(shù)資料
型號: 74LVT125PWDH
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: 3.3V Quad buffer 3-State
中文描述: LVT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
文件頁數(shù): 1/15頁
文件大?。?/td> 93K
代理商: 74LVT125PWDH
1.
General description
The LVT125 is a high-performance BiCMOS product designed for V
CC
operation at 3.3 V.
This device combines low static and dynamic power dissipation with high speed and high
output drive. The 74LVT125 device is a quad buffer that is ideal for driving bus lines. The
device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each controlling one
of the 3-state outputs.
2.
Features
I
Quad bus interface
I
3-state buffers
I
Output capability: +64 mA and
32 mA
I
TTL input and output switching levels
I
Input and output interface capability to systems at 5 V supply
I
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
I
Live insertion and extraction permitted
I
No bus current loading when output is tied to 5 V bus
I
Power-up 3-state
I
Latch-up protection:
N
JESD78: exceeds 500 mA
I
ESD protection:
N
MIL STD 883 method 3015: exceeds 2000 V
N
Machine model: exceeds 200 V
3.
Quick reference data
74LVT125
3.3 V quad buffer; 3-state
Rev. 05 — 10 February 2005
Product data sheet
Table 1:
GND = 0 V; T
amb
= 25
°
C.
Symbol Parameter
t
PLH
propagation delay nA to nY C
L
= 50 pF; V
CC
= 3.3 V
t
PHL
propagation delay nA to nY C
L
= 50 pF; V
CC
= 3.3 V
C
I
input capacitance
C
O
output capacitance
Quick reference data
Conditions
Min
-
-
-
-
Typ
2.7
2.9
4
8
Max
-
-
-
-
Unit
ns
ns
pF
pF
V
I
= 0 V or 3.0 V
outputs disabled;
V
O
= 0 V or 3.0 V
outputs disabled;
V
CC
= 3.6 V
I
CC
quiescent supply current
-
0.13
-
mA
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