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參數(shù)資料
| 型號(hào)： | 74LVT373SJX |
| 廠(chǎng)商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LATCH TRANSP OCT 3ST 20SOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | 74LVT |
| 邏輯類(lèi)型： | D 型透明鎖存器 |
| 電路： | 8:8 |
| 輸出類(lèi)型： | 三態(tài) |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 獨(dú)立電路： | 1 |
| 延遲時(shí)間 - 傳輸： | 1.5ns |
| 輸出電流高，低： | 32mA，64mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC |
| 包裝： | 帶卷 (TR) |
74L
VT373,
74L
VTH373
—
Lo
w
V
olta
g
e
Octal
T
ransparent
Latc
h
with
3-ST
A
TE
Outputs
1999 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVT373, 74LVTH373 Rev. 1.5.0
February 2008
74LVT373, 74LVTH373
Low Voltage Octal Transparent Latch with 3-STATE Outputs
Features
■ Input and output interface capability to systems at
5V VCC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH373),
also available without bushold feature (74LVT373)
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free
bus loading
■ Outputs source/sink –32 mA/+64 mA
■ Functionally compatible with the 74 series 373
■ ESD performance:
– Human-body model
> 2000V
– Machine model
> 200V
– Charged-device model
> 1000V
General Description
The LVT373 and LVTH373 consist of eight latches with
3-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch
Enable (LE) is HIGH. When LE is LOW, the data satisfy-
ing the input timing requirements is latched. Data
appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH, the bus output is in a high
impedance state.
The LVTH373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These octal latches are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT373 and
LVTH373 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number
Package Description
74LVT373WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVT373SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVT373MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74LVTH373WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVTH373SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH373MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVT373WM | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類(lèi)型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線(xiàn)路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVT373WM_Q | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類(lèi)型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線(xiàn)路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVT373WMX | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類(lèi)型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線(xiàn)路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVT374_ZAB3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74LVT374_ZAC3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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