參數(shù)資料
型號(hào): 74LVT573SJX
廠商: Fairchild Semiconductor
文件頁數(shù): 4/11頁
文件大?。?/td> 0K
描述: IC LATCH TRANSP OCT 3ST 20SOP
標(biāo)準(zhǔn)包裝: 2,000
系列: 74LVT
邏輯類型: D 型透明鎖存器
電路: 8:8
輸出類型: 三態(tài)
電源電壓: 2.7 V ~ 3.6 V
獨(dú)立電路: 1
延遲時(shí)間 - 傳輸: 1.5ns
輸出電流高,低: 32mA,64mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC
包裝: 帶卷 (TR)
1999 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVT573, 74LVTH573 Rev. 1.7.0
2
74L
VT573,
74L
VTH573
Lo
w
V
olta
g
e
Octal
T
ransparent
Latc
h
with
3-ST
A
TE
Outputs
Connection Diagram
Pin Description
Functional Description
The LVT573 and LVTH573 contain eight D-type latches
with 3-STATE standard outputs. When the Latch Enable
(LE) input is HIGH, data on the Dn inputs enters the
latches. In this condition the latches are transparent, i.e.,
a latch output will change state each time its D-type input
changes. When LE is LOW, the latches store the infor-
mation that was present on the D-type inputs a setup
time preceding the HIGH-to-LOW transition of LE. The
3-STATE standard outputs are controlled by the Output
Enable (OE) input. When OE is LOW, the standard out-
puts are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but
this does not interfere with entering new data into the
latches.
Logic Symbols
IEEE/IEC
Truth Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
Z
= High Impedance
X
= Immaterial
O0 = Previous O0 before HIGH to LOW transition
of Latch Enable
Pin Names
Description
D0–D7
Data Inputs
LE
Latch Enable Input
OE
Output Enable Input
O0–O7
3-STATE Latch Outputs
Inputs
Outputs
LE
OE
Dn
On
XHX
Z
HL
L
HLH
H
LL
X
O0
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