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    參數(shù)資料
    型號: 74LVTH162373
    廠商: Fairchild Semiconductor Corporation
    英文描述: Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25з Series Resistors in the Outputs
    中文描述: 低電壓16位透明鎖存器與三態(tài)輸出和25з在輸出串聯(lián)電阻
    文件頁數(shù): 1/7頁
    文件大小: 78K
    代理商: 74LVTH162373
    2000 Fairchild Semiconductor Corporation
    DS500354
    www.fairchildsemi.com
    October 2000
    Revised November 2000
    7
    O
    74LVTH162373
    Low Voltage 16-Bit Transparent Latch with
    3-STATE Outputs and
    25
    Series Resistors in the Outputs
    General Description
    The LVTH162373 contains sixteen non-inverting latches
    with 3-STATE outputs and is intended for bus oriented
    applications. The device is byte controlled. The flip-flops
    appear transparent to the data when the Latch Enable (LE)
    is HIGH. When LE is LOW, the data that meets the setup
    time is latched. Data appears on the bus when the Output
    Enable (OE) is LOW. When OE is HIGH, the outputs are in
    a high impedance state.
    The LVTH162373 is designed with equivalent 25
    series
    resistance in both the HIGH and LOW states of the output.
    This design reduces line noise in applications such as
    memory address drivers, clock drivers, and bus transceiv-
    ers/transmitters.
    The LVTH162373 data inputs include bushold, eliminating
    the need for external pull-up resistors to hold unused
    inputs.
    These latches are designed for low-voltage (3.3V) V
    CC
    applications, but with the capability to provide a TTL inter-
    face to a 5V environment. The LVTH162373 is fabricated
    with an advanced BiCMOS technology to achieve high
    speed operation similar to 5V ABT while maintaining a low
    power dissipation.
    Features
    I
    Input and output interface capability to systems at
    5V V
    CC
    I
    Bushold data inputs eliminate the need for external
    pull-up resistors to hold unused inputs
    I
    Live insertion/extraction permitted
    I
    Power Up/Down high impedance provides glitch-free
    bus loading
    I
    Outputs include equivalent series resistance of 25
    to
    make external termination resistors unnecessary and
    reduce overshoot and undershoot
    I
    Functionally compatible with the 74 series 16373
    I
    Latch-up performance exceeds 500 mA
    I
    ESD performance:
    Human-body model
    >
    2000V
    Machine model
    >
    200V
    Charged-device model
    >
    1000V
    Ordering Code:
    Note 1:
    Use this Order Number to receive devices in Tape and Reel.
    Logic Symbol
    Order Number
    Package
    Number
    MS48A
    Package Description
    74LVTH162373MEA
    48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
    [TUBES]
    48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
    [TAPE and REEL]
    48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
    [TUBES]
    48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
    [TAPE and REEL]
    74LVTH162373MEX
    (Note 1)
    74LVTH162373MTD
    MS48A
    MTD48
    74LVTH162373MTX
    (Note 1)
    MTD48
    相關(guān)PDF資料
    PDF描述
    74LVTH162373MEA Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25з Series Resistors in the Outputs
    74LVTH162373MEX Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25з Series Resistors in the Outputs
    74LVTH162373MTD Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25з Series Resistors in the Outputs
    74LVTH162373MTX Octal Bus Transceivers With 3-State Outputs 20-SOIC -40 to 85
    74LVTH240MTCX_NL Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
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