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參數(shù)資料
| 型號(hào)： | 74LVTH162374MTX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25з Series Resistors in the Outputs |
| 中文描述： | LVT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | 6.10 MM, MO-153ED, TSSOP-48 |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大?。?/td> | 472K |
| 代理商： | 74LVTH162374MTX |
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The 'LVTH162374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for
low-voltage (3.3-V) V
CC
operation, but with the capability to provide a TTL interface to a 5-V system environment.
They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working
registers.
SN54LVTH162374, SN74LVTH162374
3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS262L–JULY 1993–REVISED OCTOBER 2005
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock
(CLK), the Q outputs of the flip-flop take on the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 22-
series resistors to
reduce overshoot and undershoot.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
When V
CC
is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
2
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| 74LVTH162374GX | Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25з Series Resistors in the Outputs |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVTH162374ZQLR | 功能描述:觸發(fā)器 3.3V ABT 16B Edge- Triggered D-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74LVTH162374ZRDR | 功能描述:觸發(fā)器 3.3V ABT 16B Edge- Triggered D-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74LVTH16240_YBB3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74LVTH16240_YBB3116B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74LVTH16240DGGRE4 | 功能描述:緩沖器和線路驅(qū)動(dòng)器 3.3V ABT 16-Bit Buff/Drv W/3-St Otpt RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
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