參數(shù)資料
型號: 74LVX125MX
廠商: Fairchild Semiconductor
文件頁數(shù): 4/8頁
文件大?。?/td> 0K
描述: IC BUFFER TRI-ST QD LOW V 14SOIC
標(biāo)準(zhǔn)包裝: 1
系列: 74LVX
邏輯類型: 緩沖器/線路驅(qū)動器,非反相
元件數(shù): 4
每個元件的位元數(shù): 1
輸出電流高,低: 4mA,4mA
電源電壓: 2 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOIC
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 74LVX125MXDKR
1994 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVX125 Rev. 1.4.0
4
74L
VX125
Lo
w
V
olta
g
e
Quad
Buff
er
with
3-ST
A
TE
Outputs
AC Electrical Characteristics
Note:
3. Parameter guaranteed by design tOSLH = |tPLHm–tPLHn|, tOSHL = |tPHLm–tPHLn|
Capacitance
Note:
4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption without load.
Average operating current can be obtained by the eqation: ICC(opr.) =
Symbol
Parameter
VCC (V)
Conditions
TA = +25°C
TA = –40°C
to +85°C
Units
Min.
Typ.
Max.
Min.
Max.
tPLH, tPHL
Propagation Delay
Time, Data to
Output
2.7
CL = 15pF
5.8
10.1
1.0
13.5
ns
CL = 50pF
8.3
13.6
1.0
17.0
3.3 ± 0.3
CL = 15pF
4.4
6.2
1.0
8.5
CL = 50pF
6.9
9.7
1.0
12.0
tPZH, tPZL
Output Enable Time
2.7
CL = 15pF, RL = 1k
5.3
9.3
1.0
12.5
ns
CL = 50pF, RL = 1k
7.8
12.8
1.0
16.0
3.3 ± 0.3
CL = 15pF, RL = 1k
4.0
5.6
1.0
7.5
CL = 50pF, RL = 1k
6.5
9.1
1.0
11.0
tPHZ, tPLZ
Output Disable
Time
2.7
CL = 50pF, RL = 1k
10.0
15.7
1.0
19.0
ns
3.3 ± 0.3
CL = 50pF, RL = 1k
8.3
11.2
1.0
13.0
tOSHL, tOSLH Output to Output
Skew(3)
2.7
CL = 50pF
1.5
ns
3.3
1.5
Symbol
Parameter
TA = +25°C
TA = –40°C to
+85°C
Units
Min.
Typ.
Max.
Min.
Max.
CIN
Input Capacitance
4
10
pF
CPD
Power Dissipation Capacitance(4)
14
pF
C
PD
V
CC
f
IN
I
CC
×
4 per bit
,
()
---------------------------------------------------------
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