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參數(shù)資料
| 型號(hào)： | 74VCX08MTC |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC GATE AND QUAD 2IN LV 14TSSOP |
| 標(biāo)準(zhǔn)包裝： | 94 |
| 系列： | 74VCX |
| 邏輯類型： | 與門 |
| 電路數(shù)： | 4 |
| 輸入數(shù)： | 2 |
| 電源電壓： | 1.2 V ~ 3.6 V |
| 電流 - 靜態(tài)（最大值）： | 20µA |
| 輸出電流高，低： | 24mA，24mA |
| 邏輯電平 - 低： | 0.7 V ~ 0.8 V |
| 邏輯電平 - 高： | 1.6 V ~ 2 V |
| 額定電壓和最大 CL 時(shí)的最大傳播延遲： | 2.8ns @ 3.3V，30pF |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 管件 |
IDT / ICS LVCMOS/LVTTL FANOUT BUFFER
5
ICS8304AM REV. H OCTOBER 29, 2010
ICS8304
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
ADDITIVE PHASE JITTER
Additive Phase Jitter @ 125MHz
(12kHz to 20MHz) = 0.173ps typical
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
has issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB
P
HASE
N
OISE
dB
c
/H
Z
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 74VCX08MTC_08 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low Voltage Quad 2-Input AND Gate with 3.6V Tolerant Inputs and Outputs |
| 74VCX08MTC_Q | 功能描述:邏輯門 Qd 2-Input AND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74VCX08MTCX | 功能描述:邏輯門 Qd 2-Input AND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74VCX08MTCX_NL | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low Voltage Quad 2-Input AND Gate with 3.6V Tolerant Inputs and Outputs |
| 74VCX08MX | 功能描述:邏輯門 Qd 2-Input AND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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