參數(shù)資料
型號(hào): 74VHC02TTR
廠商: 意法半導(dǎo)體
英文描述: Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85
中文描述: 四2輸入或非門
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 164K
代理商: 74VHC02TTR
1/8
June 2001
I
HIGH SPEED: t
PD
= 3.6ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 2
μ
A (MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 02
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.8V (MAX.)
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I
I
I
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I
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DESCRIPTION
The 74VHC02 is an advanced high-speed CMOS
QUAD 2-INPUT NOR GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
The internal circuit is composed of 3 stages
including buffer output, which provides high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC02
QUAD 2-INPUT NOR GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
TSSOP
74VHC02M
74VHC02MTR
74VHC02TTR
TSSOP
SOP
相關(guān)PDF資料
PDF描述
74VHC02 Quad 2-Input NOR Gate
74VHC02M Quad 2-Input NOR Gate
74VHC02MTC Quad 2-Input NOR Gate
74VHC02MTCX Quad 2-Input NOR Gate
74VHC02MTCX_NL Quad 2-Input NOR Gate
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