參數資料
型號: 74VHC164SJ
廠商: Fairchild Semiconductor
文件頁數: 6/10頁
文件大?。?/td> 0K
描述: IC SHIFT REGISTER 8BIT 14SOP
標準包裝: 47
系列: 74VHC
邏輯類型: 移位寄存器
輸出類型: 標準
元件數: 1
每個元件的位元數: 8
功能: 串行至并行
電源電壓: 2 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.209",5.30mm 寬)
供應商設備封裝: 14-SOIC
包裝: 管件
1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC164 Rev. 1.4.0
5
74VHC164
8-Bit
Serial-In,
P
arallel-Out
Shift
Register
AC Electrical Characteristics
Note:
3. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained from the equation:
ICC (opr.) = CPD VCC fIN + ICC.
AC Operating Requirements
Note:
4. VCC is 3.3 ± 0.3V or 5.0 ± 0.5V
Symbol
Parameter
VCC (V)
Conditions
TA = 25°C
TA = –40°C
to +85°C
Units
Min.
Typ.
Max.
Min.
Max.
fMAX
Maximum Clock
Frequency
3.3 ± 0.3
CL = 15pF, RL = 1k
80
125
65
MHz
CL = 50pF, RL = 1k
50
75
45
5.0 ± 0.5
CL = 15pF, RL = 1k
125
175
105
CL = 50pF, RL = 1k
85
115
75
tPLH, tPHL Propagation Delay
Time (CP–Qn)
3.3 ± 0.3
CL = 15pF, RL = 1k
8.4
12.8
1.0
15.0
ns
CL = 50pF, RL = 1k
10.9
16.3
1.0
18.5
5.0 ± 0.5
CL = 15pF, RL = 1k
5.8
9.0
1.0
10.5
CL = 50pF, RL = 1k
7.3
11.0
1.0
12.5
tPHL
Propagation Delay
Time (MR–Qn)
3.3 ± 0.3
CL = 15pF, RL = 1k
8.3
12.8
1.0
15.0
ns
CL = 50pF, RL = 1k
10.8
16.3
1.0
18.5
5.0 ± 0.5
CL = 15pF, RL = 1k
5.2
8.6
1.0
10.0
CL = 50pF, RL = 1k
6.7
10.6
1.0
12.0
CIN
Input Capacitance
VCC = Open
4
10
pF
CPD
Power Dissipation
Capacitance
(3)
76
pF
Symbol
Parameter
VCC (V)
(4)
TA = 25°C
TA = –40°C
to +85°C
Units
Typ.
Guaranteed
Minimum
tW(L), tW(H)
Minimum Pulse Width (CP)
3.3
5.0
ns
5.0
tW(L)
Minimum Pulse Width (MR)
3.3
5.0
ns
5.0
tS
Minimum Setup Time
3.3
5.0
6.0
ns
5.0
4.5
tH
Minimum Hold Time
3.3
0.0
ns
5.0
1.0
tREC
Minimum Removal Time (MR)
3.3
2.5
ns
5.0
2.5
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