參數(shù)資料
型號(hào): 74VHC374SJX
廠商: Fairchild Semiconductor
文件頁數(shù): 2/9頁
文件大?。?/td> 0K
描述: IC FLIP FLOP OCT D 3ST 20SOP
標(biāo)準(zhǔn)包裝: 2,000
系列: 74VHC
功能: 標(biāo)準(zhǔn)
類型: D 型總線
輸出類型: 三態(tài)非反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
頻率 - 時(shí)鐘: 185MHz
延遲時(shí)間 - 傳輸: 5.4ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 8mA,8mA
電源電壓: 2 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
74VHC374
Octal
D-T
ype
Flip-Flop
with
3-ST
A
TE
Outputs
1992 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC374 Rev. 1.3
2
Logic Symbol
IEEE/IEC
Truth Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
Z
= High Impedance
= LOW-to-HIGH Transition
Functional Description
The VHC374 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the con-
tents of the eight flip-flops are available at the outputs.
When the OE is HIGH, the outputs go to the high imped-
ance state. Operation of the OE input does not affect the
state of the flip-flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
Figure 1.
Inputs
Outputs
Dn
CP
OE
On
HL
H
LL
L
XX
HZ
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