參數(shù)資料
型號(hào): 74VHC74MX
廠商: Fairchild Semiconductor
文件頁(yè)數(shù): 6/10頁(yè)
文件大?。?/td> 0K
描述: IC FLIP FLOP DUAL D HS 14SOIC
標(biāo)準(zhǔn)包裝: 1
系列: 74VHC
功能: 設(shè)置(預(yù)設(shè))和復(fù)位
類型: D 型
輸出類型: 差分
元件數(shù): 2
每個(gè)元件的位元數(shù): 1
頻率 - 時(shí)鐘: 170MHz
延遲時(shí)間 - 傳輸: 4.6ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 8mA,8mA
電源電壓: 2 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 74VHC74MXDKR
1992 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC74
Dual
D-T
ype
Flip-Flop
with
Preset
and
Clear
AC Electrical Characteristics
Note:
3. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained from the equation:
ICC (opr.) = CPD VCC fIN + ICC / 2 (per F/F).
AC Operating Requirements
Note:
4. VCC is 3.3 ± 0.3V or 5.0 ± 0.5V
Symbol
Parameter
VCC (V)
Conditions
TA = 25°C
TA = –40°C
to +85°C
Units
Min.
Typ.
Max.
Min.
Max.
fMAX
Maximum Clock
Frequency
3.3 ± 0.3
CL = 15pF
80
125
70
MHz
CL = 50pF
50
75
45
5.0 ± 0.5
CL = 15pF
130
170
110
CL = 50pF
90
115
75
tPLH, tPHL Propagation Delay
Time (CK-Q, Q)
3.3 ± 0.3
CL = 15pF
6.7
11.9
1.0
14.0
ns
CL = 50pF
9.2
15.4
1.0
17.5
5.0 ± 0.5
CL = 15pF
4.6
7.3
1.0
8.5
CL = 50pF
6.1
9.3
1.0
10.5
tPLH, tPHL Propagation Delay
Time (CLR, PR -Q, Q)
3.3 ± 0.3
CL = 15pF
7.6
12.3
1.0
14.5
ns
CL = 50pF
10.1
15.8
1.0
18.0
5.0 ± 0.5
CL = 15pF
4.8
7.7
1.0
9.0
CL = 50pF
6.3
9.7
1.0
11.0
CIN
Input Capacitance
VCC = Open
4
10
pF
CPD
Power Dissipation
Capacitance
(3)
25
pF
Symbol
Parameter
VCC (V)
(4)
TA = 25°C
TA = –40°C
to +85°C
Units
Typ.
Guaranteed
Minimum
tW(L), tW(H)
Minimum Pulse Width (CK)
3.3
6.0
7.0
ns
5.0
tW(L)
Minimum Pulse Width (CLR, PR)
3.3
6.0
7.0
ns
5.0
tS
Minimum Setup Time
3.3
6.0
7.0
ns
5.0
tH
Minimum Hold Time
3.3
0.5
ns
5.0
0.5
tREC
Minimum Recovery Time (CLR, PR)
3.3
5.0
ns
5.0
3.0
74VHC74 Rev. 1.3.1
5
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