參數(shù)資料
型號: 74VHCT74ATTR
廠商: 意法半導(dǎo)體
英文描述: DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
中文描述: 雙D型觸發(fā)器與預(yù)置和清除
文件頁數(shù): 1/10頁
文件大?。?/td> 73K
代理商: 74VHCT74ATTR
74VHCT74A
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
March 2000
I
HIGHSPEED:
f
MAX
=160MHz(TYP.)atV
CC
=5V
I
LOWPOWERDISSIPATION:
I
CC
=2
μ
A(MAX.) at T
A
=25
o
C
I
COMPATIBLEWITH TTL OUTPUTS:
V
IH
=2V (MIN),V
IL
= 0.8V(MAX)
I
POWERDOWN PROTECTIONON INPUTS&
OUTPUTS
I
SYMMETRICALOUTPUTIMPEDANCE:
|I
OH
| = I
OL
= 8 mA(MIN)
I
BALANCEDPROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 4.5Vto 5.5V
I
PINANDFUNCTION COMPATIBLEWITH
74SERIES74
I
IMPROVEDLATCH-UP IMMUNITY
DESCRIPTION
The 74VHCT74A is an advanced high-speed
CMOS
DUAL
D-TYPE
PRESET AND CLEAR fabricated with sub-micron
silicon gate and double-layermetal wiring C
2
MOS
technology.
A signal on the D INPUT is transfered to the Q
OUTPUT during the positive going transition of
FLIP
FLOP
WITH
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriateinput.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface5V to 3V.
All
inputs
and
outputs are
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
equipped with
PIN CONNECTION AND IEC LOGIC SYMBOLS
SOP
TSSOP
ORDER CODES
TUBE
74VHCT74AM
PACKAGE
SOP
TSSOP
T & R
74VHCT74AMTR
74VHCT74ATTR
1/10
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