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| 型號： | 7531GROUP |
| 英文描述： | 250MA CMOS LDO, ISUPPLY 1UA & 2% VOUT ACCURACY, -40C to +125C, 3-SOT-89, T/R |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 26/64頁 |
| 文件大?。?/td> | 633K |
| 代理商： | 7531GROUP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7531 Group
MITSUBISHI MICROCOMPUTERS
26
A-D Converter
The functional blocks of the A-D converter are described below.
[A-D conversion register] AD
The A-D conversion register is a read-only register that stores the
result of A-D conversion. Do not read out this register during an A-D
conversion.
[A-D control register] ADCON
The A-D control register controls the A-D converter. Bit 2 to 0 are
analog input pin selection bits. Bit 4 is the AD conversion completion
bit. The value of this bit remains at “0” during A-D conversion, and
changes to “1” at completion of A-D conversion.
A-D conversion is started by setting this bit to “0”.
[Comparison voltage generator]
The comparison voltage generator divides the voltage between V
SS
and V
REF
by 1024 by a resistor ladder, and outputs the divided volt-
ages. Since the generator is disconnected from V
REF
pin and V
SS
pin, current is not flowing into the resistor ladder.
[Channel Selector]
The channel selector selects one of ports P2
7
/AN
7
to P2
0
/AN
0,
and
inputs the voltage to the comparator.
[Comparator and control circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores its result into the A-D
conversion register. When A-D conversion is completed, the control
circuit sets the AD conversion completion bit and the AD interrupt
request bit to “1”. Because the comparator is constructed linked to a
capacitor, set f(X
IN
) to 500 kHz or more during A-D conversion.
Fig. 30 Structure of A-D control register
Fig. 31 Structure of A-D conversion register
Fig. 32 Block diagram of A-D converter
A-D control register
(ADCON : address 0034
16
, initial value: 10
16
)
Not used (returns “0” when read)
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Not used (returns “0” when read)
b7 b0
Analog input pin selection bits
000 : P2
0
/AN
0
001 : P2
1
/AN
1
010 : P2
2
/AN
2
011 : P2
3
/AN
3
100 : P2
4
/AN
4
101 : P2
5
/AN
5
110 : P2
6
/AN
6
(Note)
111 : P2
7
/AN
7
(Note)
Note:
These can be used only for 36 pin version.
Read 8-bit (Read only address 0035
16
)
b7
b0
b9
b8
b7
b6
b5
b4
b3
b2
(Address 0035
16
)
Read 10-bit (read in order address 0036
16
, 0035
16
)
b7
b0
b9
b8
(Address 0036
16
)
b7
b0
b7
b6
b5
b4
b3
b2
b1
b0
(Address 0035
16
)
Note:
High-order 6-bit of address 0036
16
returns “0” when read.
A-D control register
(Address 0034
16
)
C
A-D control circuit
Resistor ladder
V
REF
V
SS
Comparator
A-D interrupt request
b7
b0
Data bus
3
10
P2
0
/AN
0
P2
1
/AN
1
P2
2
/AN
2
P2
3
/AN
3
P2
4
/AN
4
P2
5
/AN
5
P2
6
/AN
6
P2
7
/AN
7
A-D conversion register (low-order)
(Address 0036
16
)
(Address 0035
16
)
A-D conversion register (high-order)
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