參數(shù)資料
型號(hào)： 75418-EP
廠商： Texas Instruments, Inc.
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS
中文描述： 電源良好快速瞬態(tài)響應(yīng)2 -低壓差電壓調(diào)節(jié)器
文件頁(yè)數(shù)： 17/27頁(yè)
文件大?。?/td> 388K
代理商： 75418-EP
TPS75201-EP TPS75215-EP TPS75218-EP TPS75225-EP TPS75233-EP WITH RESET
TPS75401-EP
’
75415-EP
’
75418-EP
’
75425-EP
’
75433-EP WITH POWER GOOD
FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS
SGLS165
–
APRIL 2003
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
In most cases one can neglect the effect of inductive impedance ESL. Therefore, the following application focuses
mainly on the parasitic resistance ESR.
Figure 22 shows the output capacitor and its parasitic impedances in a typical LDO output stage.
LDO
V
I
V
ESR
I
O
R
ESR
C
O
R
LOAD
V
O
+
–
Figure 22. LDO Output Stage With Parasitic Resistances ESR and ESL
In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across the
capacitor is the same as the output voltage (V(C
O
) = V
O
). This means no current is flowing into the C
O
branch. If
I
O
suddenly increases (transient condition), the following occurs:
The LDO is not able to supply the sudden current need due to its response time (t
1
in Figure 24). Therefore,
capacitor C
O
provides the current for the new load condition (dashed arrow). C
O
now acts like a battery with
an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at R
ESR
.
This voltage is shown as V
ESR
in Figure 23.
When C
O
is conducting current to the load, initial voltage at the load will be V
O
= V(C
O
)
–
V
ESR
. Due to the
discharge of C
O
, the output voltage V
O
will drop continuously until the response time t
1
of the LDO is reached
and the LDO will resume supplying the load. From this point, the output voltage starts rising again until it reaches
the regulated voltage. This period is shown as t
2
in Figure 24.
The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels
of ESRs where number 1 displays the lowest and number 3 displays the highest ESR.
From above, the following conclusions can be drawn:
The higher the ESR, the larger the droop at the beginning of load transient.
The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the LDO
response period.
相關(guān)PDF資料
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