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參數(shù)資料
| 型號： | 7542 |
| 英文描述： | 250mA CMOS LDO, lsupply 1uA and 2% Vout Accuracy, -40C to +125C, 3-SOT-23, T/R |
| 中文描述： | 7542群時鐘異步串行I / OApplication注意70K/MAY.22.03 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大小： | 70K |
| 代理商： | 7542 |
May 2003
7542 Group
Clock Asynchronous Serial I/O (UART)
Page 4 of 8
REJ05B0023-0100Z
Figure 2 Setting method for UART of serial I/O1 (2)
b7
b0
0 0
b7
b0
1
1
Process 5: When BRG output/16 is selected as synchronous clock, set value to baud rate generator.
Baud rate generator1 (BRG1) [Address 1C
16
]
Set baud rate value
Process 4: Set UART control register.
Select character length
0: 8 bits
1: 7 bits
Select parity enable
0: Parity disabled
1: Parity enabled
Select parity (valid only when parity is enabled)
0: Even parity
1: Odd parity
Select stop bit length
0: 1 stop bit
1: 2 stop bits
Select P1
1
/TxD
1
P-channel output disable (in output mode)
0: CMOS output
1: N-channel open-drain output
UART1 control register (UART1CON) [Address 1B
16
]
b7
b0
Process 8: When transmitting, start serial data transmission (
Note
).
Transmit/Receive buffer register1 (TB1/RB1) [Address 18
16
]
Set transmit data
Process 6: In order not to execute the no requested interrupt processing, set “0” (no requested)
to the serial I/O1 transmit/receive interrupt request bit.
Interrupt request register 1 (IREQ1) [Address 3C
16
]
No serial I/O1 receive interrupt request issued
No serial I/O1 transmit interrupt request issued
Serial I/O1 receive interrupt enabled
Serial I/O1 transmit interrupt enabled
Interrupt control register 1 (ICON1) [Address 3E
16
]
Process 7: When the interrupt is used, set “1” (interrupt enabled) to the serial I/O1 transmit/
receive interrupt enable bit.
Note:
When data transmission is executed at the state that an external clock input is
selected as the synchronous clock, set the transmit data while the S
CLK1
is “H” state.
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