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參數(shù)資料
| 型號： | 75C1406 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TRIPLE LOW-POWER DRIVERS/RECEIVERS |
| 中文描述： | 三重低功率驅(qū)動(dòng)器/接收器 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 126K |
| 代理商： | 75C1406 |
SN75C1406
TRIPLE LOW-POWER DRIVERS/RECEIVERS
SLLS148D – MAY 1990 – REVISED DECEMBER 1999
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VSS
RL
VCC
VDD
CL
(see Note A)
Input
Input
Output
50%
50%
10%
90%
tPLH
tPHL
tTHL
tTLH
VOH
VOL
4 V
0 V
50%
10%
90%
50%
TEST CIRCUIT
VOLTAGE WAVEFORMS
Pulse
Generator
(See Note B)
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: tw = 25
μ
s, PRR = 20 kHz, ZO = 50
, tr = tf < 50 ns.
Figure 6. Receiver Test Circuit and Voltage Waveforms
APPLICATION INFORMATION
The TIA/EIA-232-F specification is for data interchange between a host computer and a peripheral at signaling
rates up to 20 kbit/s. Many TIA/EIA-232-F devices will operate at higher data rates with lower capacitive loads
(short cables). For reliable operation at greater than 20 kbit/s, the designer needs to have control of both ends
of the cable. By mixing different types of TIA/EIA-232-F devices and cable lengths, errors can occur at higher
frequencies (above 20 kbit/s). When operating within the TIA/EIA-232-F requirements of less than 20 kbit/s and
with compliant line circuits, interoperability is assured. For applications operating above 20 kbit/s, the design
engineer should consider devices and system designs that meet the TIA/EIA-232-F requirements.
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