參數(shù)資料
型號(hào)： 7805ALPRPFB
廠商： MAXWELL TECHNOLOGIES
元件分類(lèi)： ADC
英文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, DFP28
封裝： RAD-PAK, LDFP-28
文件頁(yè)數(shù)： 31/34頁(yè)
文件大小： 605K
代理商： 7805ALPRPFB
Memory
PRELIMINARY
6
All data sheets are subject to change without notice
2001 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
7805ALP
12.19.01 Rev 6
1000583
TABLE 13. 7805ALP TEMPERATURE
PARAMETER
MIN
TYP
MAX
UNIT
Specified Performance
-40
--
85
°
C
Derated Performance 1
1. Tested by application of signal.
-55
--
125
°
C
Storage
-65
--
150
°
C
TABLE 14. 7805ALP CONVERSION TIMING1
1. Tested by application of signal.
DESCRIPTION
SYMBOL
MIN
TYP
MAX
UNIT
Convert pulse width
t
1
40
--
7000
ns
Data valid delay after R/C low
t
2
--
8
s
BUSY delay from R/C low
t
3
--
85
ns
BUSY low
t
4
--
8
s
BUSY delay after end-of-conversion
t
5
--
220
--
ns
Aperture time
t
6
--
40
--
ns
Conversion time
t
7
--
7.6
8
s
Acquisition time
t
8
--
2
s
Bus relinquish time
t
9
10
35
83
ns
BUSY delay after data valid
t
10
50
200
--
ns
Previous data valid delay after R/C low
t
11
--
7.4
--
s
Throughput time
t
7 + t8
--
9
10
s
R/C to CS setup time
t
12
10
--
ns
Time between conversions
t
13
10
--
s
Bus access time
t
14
10
--
83
ns
TABLE 15. 7805ALP CONTROL LINE FUNCTION FOR READ AND CONVERT
CS
R/C
BUSY
OPERATION
1
X
None. Databus is in Hi-Z state.
↓
0
1
Initiates conversion "n". Databus remains in Hi-Z state.
0
↓
1
Initiates conversion "n". Databus enters Hi-Z state.
01
↓
Conversion "n" completed. Valid data from conversion "n" on the databus.
↓
1
Enables databus with valid data from conversion "n".
↓
1
0
Enables databus with valid data from conversion "n-1". Conversion "n" in progress.
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