Memory
PRELIMINARY
27
All data sheets are subject to change without notice
2001 Maxwell Technologies
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16-Bit Latchup Protected ADC
7805ALP
12.19.01 Rev 6
1000583
MODE = 1, address inputs (A2, A1, A0) select desired channel.
Write XXX Hex With MODE = 1 all data writes are to the selected DAC. XXX is the required data. 200
Hex will give zero scale and 1FF Hex will give full scale from the DAC.
Table 20 and Figure 21 show the analog outputs available for the above configuration. The following is the procedure
required if the complete transfer function needs to be offset around the VBIAS point. Table 21 and Figure 22 show the
analog output variations available from the Sub DAC.
System Control Register Write:
MODE = 0, address inputs (A2, A1, A0) are don’t cares.
Write 020 Hex
Configure part for 10-bit parallel, twos complement coding, normal operation
Channel Control Register Write:
MODE = 0, address inputs (A2, A1, A0) select desired channel.
Write 091 Hex
Internal VDD/2 selected as VBIAS for DAC, and any DAC data writes that follow are to
the Sub DAC.
DAC Data Register Write:
MODE = 1, address inputs (A2, A1, A0) select desired channel.
Write XX Hex With MODE = 1 all data writes are to the selected DACs Sub DAC. XX is the required data.
7F Hex will give zero scale and 80 Hex will give full scale from the Sub DAC.
Channel Control Register Write:
MODE = 0, address inputs (A2, A1, A0) select desired channel.
Write 011 Hex
Internal VDD/2 selected as VBIAS for DAC, and any DAC data writes that follow are to
the Main DAC.
DAC Data Register Write:
MODE = 1, address inputs (A2, A1, A0) select desired channel.
Write XXX Hex With MODE = 1 all data writes are to the selected Main DAC. XXX is the required data.
1FF Hex will give zero scale and 200 Hex will give full scale from the DAC.
OFFSET BINARY CODING
Table 22 shows the offset binary transfer function for the Main DAC.