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參數(shù)資料
| 型號： | 7846RPFE |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 16-BIT DAC, DFP28 |
| 封裝： | RAD-PAK, LDFP-28 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 214K |
| 代理商： | 7846RPFE |
Memory
6
All data sheets are subject to change without notice
2002 Maxwell Technologies
All rights reserved.
16-Bit Digital to Analog Converter
7846
02.19.02 Rev 4
TABLE 6. 7846 TIMING CHARACTERISTICS1,2,3,4
(V
DD = +14.25V TO 15.75V; VSS = -14.25V TO -15.75V; VCC = 4.75 TO 5.25V; UNLESS OTHERWISE SPECIFIED)
1. Guaranteed by design. All input control signals are specified with t
R = tF = 5ns (10% to 90% of +5V) and timed from a voltage
level of 1.6V.
2. t
6 is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
3. t
7 is defined as the time required for an output to change 0.5V when loaded with the circuits of Figure 2. Specifications subject to
change without notice.
4. See Figure 3 on page 7.
PARAMETER
TEST CONDITIONS/COMMENTS
LIMIT AT
T
A=-55
°
C TO +125 °C
UNIT
t
1
R/W to CS Setup Time
50
ns min
t
2
CS Pulse Width (Write Cycle)
190
ns min
t
3
R/W to CS Hold Time
50
ns min
t
4
Data Setup Time
120
ns min
t
5
Data Hold Time
0
ns min
t
6
Data Access Time
320
ns max
t
7
Bus Relinquish Time
10
ns min
90
ns max
t
8
CLR Setup Time
20
ns min
t
9
CLR Pulse Width
150
ns min
t
10
CLR Hold Time
0
ns min
t
11
LDAC Pulse Width
100
ns min
t
12
CS Pulse Width (Read Cycle)
330
ns min
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