2006 Teridian Semiconductor Corporation Rev." />
參數(shù)資料
型號: 78P2351-DB-CMI
廠商: Maxim Integrated Products
文件頁數(shù): 7/42頁
文件大小: 0K
描述: DEMO BOARD 78P2351
標準包裝: 1
系列: *
78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
Page: 15 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
REGISTER DESCRIPTION (continued)
ADDRESS 1-2: ADVANCED TRANSMIT CONTROL REGISTER 1
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7:1
--
R/W
0000000
Reserved.
0
TXEQ
R/W
0
Transmit Fixed Equalizer Enable:
When enabled, compensates for between 0.75m and 1.5m of FR4
trace to the serial LVPECL data inputs SIDP/N
0: Normal Operation
1: Enable equalizer
ADDRESS 1-3: ADVANCED TRANSMIT CONTROL REGISTER 0
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7:3
--
R/W
10101
Reserved.
2:1
BST[1:0]
R/W
00
Transmit Driver Amplitude Boost:
Adds roughly 5% or 10% of boost to the CMI output. Limits not tested
during production test.
00 : Normal amplitude
01 : 5% boost
10 : Reserved
11 : 10% boost
0
FLBK
R/W
0
Full Remote (digital) Loopback Enable:
When enabled the recovered receive data is decoded and looped back
to the transmit clock recovery unit exercising the entire receive and
transmit paths.
NOTE: Must be used in conjunction with Serial Plesiochronous Mode or
Serial Loop-Timing Mode.
ADDRESS 1-4: MODE CONTROL REGISTER 2
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7
CMI
R/W
1
Line Interface Mode Selection:
0: Optical fiber (LVPECL, NRZ). CMI ENDEC and line driver are
disabled. Use RXP/N and ECLP/N pins for line interface.
1: Coaxial cable (CMI encoded). CMI ENDEC enabled. Optical
(NRZ) interface disabled. Use RXP/N and CMIP/N pins for line
interface.
6:0
--
R/W
XX00000
Reserved.
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