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參數(shù)資料
| 型號： | 78Q2133R/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 36/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX 10/100 MDIX 3.3V IND 32-QFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | PHY 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | IEEE 802 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設(shè)備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 帶卷 (TR) |
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DS_21x3_001
78Q2123/78Q2133 Data Sheet
Rev. 1.6
7
The received MLT-3 signal is converted to 5 bit NRZ code groups and output from the RX_ER and
RXD[3:0] pins, RX_ER being the MSB of the data output. The RX_DV and TX_EN pins are unused in
PCS Bypass mode.
1.3
10BASE-T OPERATION
1.3.1
10BASE-T Transmit
The 78Q2123/78Q2133 take 4-bit parallel NRZ data via the MII interface and passes it through a parallel
to serial converter. The data is then passed through a Manchester encoder, pre-emphasis pulse-shaper,
media filter, and finally to the twisted-pair line driver. The pulse-shaper and filter ensure the output
waveforms meet the voltage template and spectral content requirements detailed in Clause 14 of
IEEE-802.3. Interface to the twisted-pair media is through a center-tapped 1:1 transformer. No external
filtering is required. During auto-negotiation and 10BASE-T idle periods, link pulses are transmitted.
The 78Q2123/78Q2133 employ an onboard timer to prevent the MAC from capturing a network through
excessively long transmissions. When this timer expires, the chip enters the jabber state and
transmission is halted. The jabber state is exited after the MII goes idle for 500
±250 ms.
1.3.2
10BASE-T Receive
The 78Q2123/78Q2133 receive Manchester-encoded 10BASE-T data through the twisted pair inputs and
re-establishes logic levels through a slicer with a smart squelch function. The slicer automatically adjusts
its level after detection of valid data with the appropriate levels. Data is passed on to the CDR where the
clock is recovered, and the data is re-timed and decoded. From there, data enters the serial-to-parallel
converter for transmission to the MAC via the Media Independent Interface. Interface to the twisted-pair
media is through an external 1:1 transformer. Polarity information is detected and corrected within
internal circuitry.
1.3.3
Polarity Correction
The 78Q2123/78Q2133 are capable of either automatic or manual polarity reversal for 10BASE-T and
auto-negotiation functions. Register bits MR16.5 and MR16.4 control this feature. The default is
automatic mode where MR16.5 is low and MR16.4 indicates if the detection circuitry has inverted the
input signal. To enter manual mode, MR16.5 should be set high and MR16.4 will then control the signal
polarity.
1.3.4
SQE TEST
The 78Q2123/78Q2133 support the Signal Quality Error (SQE) function detailed in IEEE-802.3. At an
interval of 1
s after each negative transition of the TX_EN pin in 10BASE-T mode, the COL pin will go
high for a period of 1
s. SQE is not signaled during transmission after collision is detected. SQE is
automatically disabled when repeater mode is enabled. This function can be disabled through register bit
MR16.11.
1.3.5
Natural Loopback
When enabled, whenever the 78Q2123/78Q2133 are transmitting and not receiving on the twisted pair
media (10BASE-T Half Duplex mode), data on the TXD3-0 pins are looped back onto the RXD3-0 pins.
During a collision, data from the RXI pins is routed to the RXD3-0 pins. The natural loopback function is
enabled through register bit MR16.10. This feature is off by default.
1.3.6
Repeater Mode
When register bit MR16.15 is set, the 78Q2123/78Q2133 are placed in repeater mode. In this mode, full
duplex operation is prohibited, CRS responds only to receive activity and, in 10BASE-T mode, the SQE
test function is disabled.
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