參數(shù)資料
型號(hào): 78Q8430STEM#DB
廠商: Maxim Integrated Products
文件頁數(shù): 15/88頁
文件大小: 0K
描述: EVAL BOARD 78Q8430
標(biāo)準(zhǔn)包裝: 1
系列: *
78Q8430 Data Sheet
DS_8430_001
22
Rev. 1.2
5
Host Interface Timing Specification
5.1
Host Interface
CS
DATA
WR/OE
ADDR
MEMWAIT
T
SU
T
SL
T
WT
T
HWT
T
HCS
T
HO
T
L
T
H
T
HOWT
Figure 8: Host Interface Timing Diagram
Name
Description
Requirement
Min
Max
T
CS and ADDR setup time
SU
CS and ADDR must be stable on or
before the falling edge of
WR/OE.
0 ns
T
Output settling time
SL
The maximum amount of time that it will
take the MEMWAIT, or DATA when there
is no MEMWAIT, outputs to become
stable after the falling edge of
WR/OE.
13.7 ns
T
Maximum wait time
WT
The maximum amount of time that the
MEMWAIT output will held asserted.
17 ck
T
Wait hold time
HWT
The minimum amount of time that the
WR/OE input must be held past the
de-assertion of MEMWAIT.
10 ns
T
CS hold time
HCS
The
CS input must be stable low for the
entire duration of the
WR/OE low cycle.
0 ns
T
ADDR and DATA hold time
HO
The ADDR and DATA inputs must be
stable for no less than this amount of time
after the falling edge of
WR.
2.5 ck
T
WR/OE min low pulse
L
The minimum amount of time that the
WR/OE inputs must be held low.
2 ck
T
WR/OE min high pulse
H
The minimum amount of time that the
WR/OE inputs must be held high.
2 ck
Note: On read cycles when MEMWAIT is asserted the DATA outputs will be valid before the
de-assertion of MEMWAIT.
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