參數(shù)資料
型號: 79RC32334-100BBG
廠商: Integrated Device Technology, Inc.
英文描述: IDT Interprise Integrated Communications Processor
中文描述: IDT的洽談會集成通信處理器
文件頁數(shù): 9/30頁
文件大?。?/td> 467K
代理商: 79RC32334-100BBG
9 of 30
August 31, 2004
IDT 79RC32334—Rev. Y
uart_tx[1:0]
I/O
Z
Low
UART Transmit Data Bus
UART mode: Each UART channel sends data on their respective output pin. Note that these pins default
to inputs at reset time and must be programmed via the PIO interface before being used as UART out-
puts.
uart_tx[0] Alternate function: PIO[5].
uart_tx[1] Alternate function: PIO[3].
uart_cts_n[0]
uart_dsr_n[0]
uart_dtr_n[0]
uart_rts_n[0]
I/O
Z
Low
UART Transmit Data Bus
UART mode: Data bus modem control signal pins for UART channel 0.
uart_cts_n[0] Alternate function: PIO[15].
uart_dsr_n[0] Alternate function: PIO[14].
uart_dtr_n[0] Alternate function: PIO[13].
uart_rts_n[0] Alternate function: PIO[12].
spi_mosi
I/O
L
Low
SPI Data Output
Serial mode: Output pin from RC32334 as an Input to a Serial Chip for the Serial data input stream.
In PCI satellite mode, acts as an Output pin from RC32334 that connects as an Input to a Serial Chip for
the Serial data input stream for loading PCI Configuration Registers in the RC32334 Reset Initialization
Vector PCI boot mode.
1st Alternate function: PIO[10]. Defaults to the output direction at reset time.
2nd Alternate function: pci_eeprom_mdo.
spi_miso
I/O
Z
Low
SPI Data Input
Serial mode: Input pin to RC32334 from the Output of a Serial Chip for the Serial data output stream.
In PCI satellite mode, acts as an Input pin from RC32334 that connects as an output to a Serial Chip for
the Serial data output stream for loading PCI Configuration Registers in the RC32334 Reset Initialization
Vector PCI boot mode.
Defaults to input direction at reset time.
1st Alternate function: PIO[7].
2nd Alternate function: pci_eeprom_mdi.
spi_sck
I/O
L
Low
SPI Clock
Serial mode: Output pin for Serial Clock.
In PCI satellite mode, acts as an Output pin for Serial Clock for loading PCI Configuration Registers in the
RC323334 Reset Initialization Vector PCI boot mode.
1st Alternate function: PIO[9]. Defaults to the output direction at reset time.
2nd Alternate function: pci_eeprom_sk.
spi_ss_n
I/O
H
Low
SPI Chip Select
Output pin selecting the serial protocol device as opposed to the PCI satellite mode EEPROM device.
Alternate function: PIO[8]. Defaults to the output direction at reset time.
CPU Core Specific Signals
cpu_nmi_n
Input
CPU Non-Maskable Interrupt
Requires external pull-up.
This interrupt input is active low to the CPU.
cpu_masterclk
Input
CPU Master System Clock
Provides the basic system clock.
cpu_int_n[5:4], [2:0]
Input
CPU Interrupt
Requires external pull-up.
These interrupt inputs are active low to the CPU.
cpu_coldreset_n
Input
L
CPU Cold Reset
This active-low signal is asserted to the RC32334 after
V
cc
becomes valid on the initial power-up. The
Reset initialization vectors for the RC32334 are latched by cold reset.
Name
Type
Reset
State
Status
Drive
Strength
Capability
Description
Table 1 Pin Description (Part 5 of 7)
相關(guān)PDF資料
PDF描述
79RC32334-100BBGI IDT Interprise Integrated Communications Processor
79RC32334-100BBI IDT Interprise Integrated Communications Processor
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
79RC32334-100BBGI 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor
79RC32334-100BBI 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor
79RC32334-133BB 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor
79RC32334-133BBG 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor
79RC32334-133BBGI 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor