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參數資料
| 型號： | 79RC32334-150BBG |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | IDT Interprise Integrated Communications Processor |
| 中文描述： | IDT的洽談會集成通信處理器 |
| 文件頁數： | 10/30頁 |
| 文件大?。?/td> | 467K |
| 代理商： | 79RC32334-150BBG |
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10 of 30
August 31, 2004
IDT 79RC32334—Rev. Y
cpu_dt_r_n
Output
Z
—
CPU Direction Transmit/Receive
This active-low signal controls the DT/R pin of an optional FCT245 transceiver bank. It is asserted during
read operations.
1st Alternate function: mem_245_dt_r_n.
2nd Alternate function: sdram_245_dt_r_n.
JTAG Interface Signals
jtag_tck
Input
—
JTAG Test Clock
Requires external pull-down.
An input test clock used to shift into or out of the Boundary-Scan register cells. jtag_tck is independent of
the system and the processor clock with nominal 50% duty cycle.
jtag_tdi,
ejtag_dint_n
Input
—
JTAG Test Data In
Requires an external pull-up on the board.
On the rising edge of jtag_tck, serial input data are shifted into either the Instruction or Data register,
depending on the TAP controller state. During Real Mode, this input is used as an interrupt line to stop the
debug unit from Real Time mode and return the debug unit back to Run Time Mode (standard JTAG).
This pin is also used as the ejtag_dint_n signal in the EJTAG mode.
jtag_tdo,
ejtag_tpc
Output
Z
High
JTAG Test Data Out
The jtag_tdo is serial data shifted out from instruction or data register on the falling edge of jtag_tck. When
no data is shifted out, the jtag_tdo is tri-stated. During Real Time Mode, this signal provides a non-
sequential program counter at the processor clock or at a division of processor clock. This pin is also used
as the ejtag_tpc signal in the EJTAG mode.
jtag_tms
Input
—
JTAG Test Mode Select
Requires external pull-up.
The logic signal received at the jtag_tms input is decoded by the TAP controller to control test operation.
jtag_tms is sampled on the rising edge of the jtag_tck.
jtag_trst_n
Input
L
—
JTAG Test Reset
When neither JTAG nor EJTAG are being used, jtag_trst_n must be driven low (pulled down) or the
jtag_tms/ejtag_tms signals must be pulled up and jtag_clk actively clocked.
ejtag_dclk
Output
Z
—
EJTAG Test Clock
Processor Clock. During Real Time Mode, this signal is used to capture address and data from the
ejtag_tpc signal at the processor clock speed or any division of the internal pipeline.
ejtag_pcst[2:0]
I/O
Z
Low
EJTAG PC Trace Status Information
111 (STL) Pipe line Stall
110 (JMP) Branch/Jump forms with PC output
101 (BRT) Branch/Jump forms with no PC output
100 (EXP) Exception generated with an exception vector code output
011 (SEQ) Sequential performance
010 (TST) Trace is outputted at pipeline stall time
001 (TSQ) Trace trigger output at performance time
000 (DBM) Run Debug Mode
Alternate function: modebit[2:0].
ejtag_debugboot
Input
—
Requires
external pull-
down
EJTAG DebugBoot
The ejtag_debugboot input is used during reset and forces the CPU core to take a debug exception at the
end of the reset sequence instead of a reset exception. This enables the CPU to boot from the ICE probe
without having the external memory working. This input signal is level sensitive and is not latched inter-
nally. This signal will also set the JtagBrk bit in the JTAG_Control_Register[12].
ejtag_tms
Input
—
Requires
external pull-
up
EJTAG Test Mode Select
An external pull-up on the board is required.
The ejtag_tms is sampled on the rising edge of jtag_tck.
Name
Type
Reset
State
Status
Drive
Strength
Capability
Description
Table 1 Pin Description (Part 6 of 7)
相關PDF資料 |
PDF描述 |
|---|---|
| 79RC32334-150BBGI | IDT Interprise Integrated Communications Processor |
| 79RC32334-150BBI | IDT Interprise Integrated Communications Processor |
| 79RC32334 | IDT Interprise Integrated Communications Processor |
| 79RC32334-100BB | IDT Interprise Integrated Communications Processor |
| 79RC32334-100BBG | IDT Interprise Integrated Communications Processor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 79RC32334-150BBGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor |
| 79RC32334-150BBI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor |
| 79RC32351 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor |
| 79RC32351-100DH | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor |
| 79RC32351-133DH | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor |
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