參數(shù)資料
型號(hào)： 79RC32351-100DH
廠商： Integrated Device Technology, Inc.
英文描述： IDT Interprise Integrated Communications Processor
中文描述： IDT的洽談會(huì)集成通信處理器
文件頁數(shù)： 9/42頁
文件大?。?/td> 560K
代理商： 79RC32351-100DH
9 of 42
May 25, 2004
IDT 79RC32351
MIIMDIOP
I/O
Low Drive
with STI
MII Management Data.
This bidirectional signal is used to transfer data between the station management entity and the
ethernet PHY.
MIIRXCLKP
I
STI
MII Receive Clock.
This clock is a continuous clock that provides a timing reference for the reception of data.
MIIRXDP[3:0]
I
STI
MII Receive Data.
This nibble wide data bus contains the data received by the ethernet PHY.
MIIRXDVP
I
STI
MII Receive Data Valid.
The assertion of this signal indicates that valid receive data is in the MII receive data bus.
MIIRXERP
I
STI
MII Receive Error.
The assertion of this signal indicates that an error was detected somewhere in the ethernet frame cur-
rently being sent in the MII receive data bus.
MIITXCLKP
I
STI
MII Transmit Clock.
This clock is a continuous clock that provides a timing reference for the transfer of transmit data.
MIITXDP[3:0]
O
Low Drive
MII Transmit Data.
This nibble wide data bus contains the data to be transmitted.
MIITXENP
O
Low Drive
MII Transmit Enable.
The assertion of this signal indicates that data is present on the MII for transmission.
MIITXERP
O
Low Drive
MII Transmit Coding Error.
When this signal is asserted together with MIITXENP, the ethernet PHY will transmit symbols
which are not valid data or delimiters.
EJTAG
JTAG_TCK
I
STI
JTAG Clock.
This is an input test clock, used to shift data into or out of the boundary scan logic. This signal requires an
external resistor, listed in Table 14.
JTAG_TDI
I
STI
JTAG Data Input.
This is the serial data shifted into the boundary scan logic. This signal requires an external resistor,
listed in Table 14. This is also used to input EJTAG_DINTN during EJTAG/ICE mode. EJTAG_DINTN is an interrupt to
switch the PC trace mode off.
JTAG_TDO
O
Low Drive
JTAG Data Output.
This is the serial data shifted out from the boundary scan logic. When no data is being shifted out, this
signal is tri-stated. This signal requires an external resistor, listed in Table 14. This is also used to output the EJTAG_TPC
during EJTAG/ICE mode. EJTAG_TPC is the non-sequential program counter output.
JTAG_TMS
I
STI
JTAG Mode Select
. This input signal is decoded by the tap controller to control test operation. This signal requires an
external resistor, listed in Table 14.
EJTAG_PCST[0]
O
Low Drive
PC trace status.
This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected
during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal
requires an external resistor, listed in Table 14.
Primary function: General Purpose I/O, GPIOP[10].
1st Alternate function: UART channel 1 data terminal ready, U1DTRN.
EJTAG_PCST[1]
O
Low Drive
PC trace status.
This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected
during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal
requires an external resistor, listed in Table 14.
Primary function: General Purpose I/O, GPIOP[11]. At reset, this pin defaults to primary function GPIOP[11].
1st Alternate function: UART channel 1 data set ready, U1DSRN.
EJTAG_PCST[2]
O
Low Drive
PC trace status.
This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected
during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal
requires an external resistor, listed in Table 14.
Primary function: General Purpose I/O, GPIOP[12].
1st Alternate function: UART channel 1 request to send, U1RTSN.
EJTAG_DCLK
O
Low Drive
PC trace clock.
This is used to capture address and data during EJTAG/ICE mode. EJTAG/ICE enable is selected during
reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal requires
an external resistor, listed in Table 14.
Primary function: General Purpose I/O, GPIOP[13].
1st Alternate function: UART channel 1 clear to send, U1CTSN.
Name
Type I/O Type
Description
Table 1 Pin Descriptions (Part 5 of 7)
相關(guān)PDF資料
PDF描述
79RC32351-133DH IDT Interprise Integrated Communications Processor
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
79RC32351-133DH 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor
79RC32355 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Communications Processor
79RC32355133DH 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Communications Processor
79RC32355-133DH 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Communications Processor
79RC32355133DHI 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Communications Processor
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