參數(shù)資料
型號(hào): 79RC32K438-300BB
廠商: Integrated Device Technology, Inc.
英文描述: IDTTM InterpriseTM Integrated Communications Processor
中文描述: IDTTM InterpriseTM集成通信處理器
文件頁數(shù): 23/59頁
文件大小: 644K
代理商: 79RC32K438-300BB
23 of 59
May 25, 2004
IDT 79RC32438
Figure 7 DDR SDRAM Timing Waveform — Write Access
Signal
Symbol
Reference
Edge
200MHz
233MHz
266MHz
300MHz
Unit
Conditions
Timing
Diagram
Reference
Min
Max
Min
Max
Min
Max
Min
Max
Memory and Peripheral Bus
1
See Figures 8
and 9.
MADDR[21:0]
Tdo_8a
EXTCLK rising
0.0
5.0
0.0
5.0
0.0
5.0
0.0
5.0
ns
Tdz_8a
2
0.0
0.1
0.0
0.1
0.0
0.1
0.0
0.1
ns
Tzd_8a
2
0.5
2.3
0.5
2.3
0.5
2.3
0.5
2.3
ns
MADDR[25:22]
Tdo_8b
EXTCLK rising
0.0
6.5
0.0
6.5
0.0
6.5
0.0
6.5
ns
Tdz_8b
2
0.7
1.5
0.7
1.5
0.7
1.5
0.7
1.5
ns
Tzd_8b
2
1.2
3.3
1.2
3.3
1.2
3.3
1.2
3.3
ns
Table 8 Memory and Peripheral Bus AC Timing Characteristics (Part 1 of 3)
2
DDRDATA is either 32-bits or 16-bits wide depending on the DBW control bit in DDRC Register
(see
Chapter 7, DDR Controller, in the RC32438 User Reference Manual
).
RowA
Col A0
Col A2
NOP
ACTV
NOP
WR
WR
NOP
NOP
NOP
NOP
NOP
BNKx
BNKx
FF
DM0 DM1
DM3
FF
D0
D1 D2
D3
Tdo_7k
Tdo_7k
Tdo_7l
Tdo_7l
Tdo_7m
Tdo_7m
Tdo_7m
Tdo_7m
Tdo_7m
DDRCKPx
DDRCKNx
DDRCSNx
DDRADDR[13:0]
DDRCMD
1
DDRCKE
DDRBA[1:0]
DDROEN[3:0]
DDRDM[7:0]
DDRDQSx
DDRDATA[31:0]
2
DM2
1
DDRCMD contains DDRRASN, DDRCASN and DDRWEN.
DDRDQSx
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