參數(shù)資料
型號(hào): 79RC32T355-180DH
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: IDT Interprise Integrated Communications Processor
中文描述: 32-BIT, 180 MHz, RISC PROCESSOR, PQFP208
封裝: 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MO-143FA-1, QFP-208
文件頁數(shù): 34/47頁
文件大?。?/td> 987K
代理商: 79RC32T355-180DH
34 of 47
May 25, 2004
IDT 79RC32355
Signal
Symbol
Reference
Edge
133MHz
150MHz
180MHz
Unit
Conditions
Timing
Diagram
Reference
Min
Max
Min
Max
Min
Max
I
2
C
1
1.
For more information see the I
2
C-Bus specification by Philips Semiconductor
SCLP
Frequency
none
0
100
0
100
0
100
kHz
100 KHz
Figure 18
Thigh1
4.0
4.0
4.0
μ
s
Tlow1
4.7
4.7
4.7
μ
s
Trise1
1000
1000
1000
ns
Tfall1
300
300
300
ns
SDAP
Tsu2
SCLP rising
250
250
250
ns
Thld2
0
3.45
0
3.45
0
3.45
μ
s
Trise2
1000
1000
1000
ns
Tfall2
300
300
300
ns
Start or repeated start condition
Tsu3
SDAP falling
4.7
4.7
4.7
μ
s
Thld3
4.0
4.0
4.0
μ
s
Stop condition
Tsu4
SDAP rising
4.0
4.0
4.0
μ
s
Bus free time between a stop and
start condition
Tdelay5
4.7
4.7
4.7
μ
s
SCLP
Frequency
none
0
400
0
400
0
400
kHz
400 KHz
Thigh1
0.6
0.6
0.6
μ
s
Tlow1
1.3
1.3
1.3
μ
s
Trise1
300
300
300
ns
Tfall1
300
300
300
ns
SDAP
Tsu2
SCLP rising
100
100
100
ns
Thld2
0
0.9
0
0.9
0
0.9
μ
s
Trise2
300
300
300
ns
Tfall2
300
300
300
ns
Start or repeated start condition
Tsu3
SDAP falling
0.6
0.6
0.6
μ
s
Thld3
0.6
0.6
0.6
μ
s
Stop condition
Tsu4
SDAP rising
0.6
0.6
0.6
μ
s
Bus free time between a stop and
start condition
Tdelay5
1.3
1.3
1.3
μ
s
Table 13 I
2
C AC Timing Characteristics
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