參數(shù)資料
型號(hào): 79RC32T355150DHI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: Communications Processor
中文描述: 32-BIT, 150 MHz, RISC PROCESSOR, PQFP208
封裝: 28 X 28 MM, 3.40 MM HEIGHT, MO-143FA1, PLASTIC, QFP-208
文件頁數(shù): 36/47頁
文件大小: 987K
代理商: 79RC32T355150DHI
36 of 47
May 25, 2004
IDT 79RC32355
Table 15 JTAG AC Timing Characteristics
Figure 20 JTAG AC Timing Waveform
Signal
Symbol
Reference
Edge
133MHz
150MHz
180MHz
Unit
Conditions
Timing
Diagram
Reference
Min
Max
Min
Max
Min
Max
EJTAG and JTAG
JTAG_TCK
Tperiod1
none
100
100
100
ns
Figure 20
Thigh1, Tlow1
40
40
40
ns
Trise1, Tfall1
5
5
5
ns
EJTAG_DCLK
1
1.
EJTAG_DCLK is equal to the internal CPU pipeline clock.
2.
A negative delay denotes the amount of time before the reference clock edge.
Tperiod2
none
7.5
10.0
6.7
10.0
5.6
10.0
ns
Thigh2, Tlow2
2.5
2.5
2.5
ns
Trise2, Tfall2
3.5
3.5
3.5
ns
JTAG_TMS, JTAG_TDI,
JTAG_TRST_N
Tsu3
JTAG_TCK rising
3.0
3.0
3.0
ns
Thld3
1.0
1.0
1.0
ns
JTAG_TDO
Tdo4
JTAG_TCK falling
2.0
12.0
2
12.0
2
12.0
ns
Tdo5
EJTAG_DCLK rising
-0.7
2
1.0
-0.7
2
1.0
-0.7
2
1.0
ns
JTAG_TRST_N
Tpw6
none
100
100
100
ns
Tsu6
JTAG_TCK rising
2
2
2
ns
EJTAG_PCST[2:0]
Tdo7
EJTAG_DCLK rising
-0.3
2
3.3
-0.3
2
3.3
-0.3
2
3.3
ns
Tperiod1
Tfall1
Tlow1
Thigh1
Trise2
Tfall2
Thigh2
Tlow2
Tsu3
Thld3
Tdo4
Tperiod2
Trise1
Tdo5
Tdo7
Tsu6
Tpw6
JTAG_TCK
EJTAG_DCLK
JTAG_TMS,
JTAG_TDI
JTAG_TDO
EJTAG_PCST
JTAG_TRST_N
EJTAG_TRST_N
TPC
TDO
TDO
PCST
EJTAG TPC, TCST capture
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