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參數(shù)資料
| 型號： | 7ABT2952PWDH |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal registered transceiver 3-State |
| 中文描述： | 登記收發(fā)器八路三態(tài) |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 110K |
| 代理商： | 7ABT2952PWDH |
Philips Semiconductors
Product specification
74ABT2952
Octal registered transceiver (3-State)
1998 Feb 11
6
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
°
C
V
CC
= +5.0V
T
amb
= –40
°
C to +85
°
C
V
CC
= +5.0V
±
0.5V
UNIT
Min
Typ
Min
t
S
(H)
t
s
(L)
Setup time
An to CPAB or Bn to CPBA
2
4.5
3.5
2.2
1.6
4.5
3.5
ns
t
h
(H)
t
h
(L)
Hold time
An to CPAB or Bn to CPBA
2
0.0
0.0
–0.8
–1.4
0.0
0.0
ns
t
s
(H)
t
s
(L)
Setup time
CEAB to CPAB, CEBA to CPBA
2
4.0
3.0
0.8
0.8
4.0
3.0
ns
t
h
(H)
t
h
(L)
Hold time
CEAB to CPAB, CEBA to CPBA
2
0.0
0.0
–0.7
–0.7
0.0
0.0
ns
t
w
(H)
t
w
(L)
CPAB or CPBA pulse width,
High or Low
1
3.0
3.5
0.8
0.9
3.0
3.5
ns
AC WAVEFORMS
V
M
= 1.5V, V
IN
= GND to 3.0V
V
M
V
M
V
M
V
M
V
M
1/f
MAX
t
w
(H)
t
PHL
t
w
(L)
t
PLH
CPBA or
CPAB
An or Bn
SA00087
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
ééé
ééééééééé
ééééééééé
ééééééééé
V
M
An, Bn
CEAB,
CEBA
V
M
V
M
V
M
M
M
CPAB,
CPBA
t
s
(H)
t
h
(H)
t
s
(L)
t
h
(L)
SA00118
Waveform 2. Data Setup and Hold Times
OEAB,
OEBA
V
M
t
PZH
t
PHZ
0V
V
OH
–0.3V
An, Bn
V
M
V
M
SA00119
V
OH
Waveform 3. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
OEAB,
OEBA
t
PZL
t
PLZ
V
OL
V
OL
+0.3V
An, Bn
V
M
V
M
V
M
SA00120
Waveform 4. 3–State Output Enable Time to Low Level and
Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORMS
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