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參數(shù)資料
| 型號： | 7AHCT374PWDH |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal D-type flip-flop; positive edge-trigger; 3-state |
| 中文描述： | 八路D型觸發(fā)器，上升沿觸發(fā)，三態(tài) |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 93K |
| 代理商： | 7AHCT374PWDH |
1999 Sep 28
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC374;
74AHCT374
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger
actions
Inputsacceptsvoltageshigherthan
V
CC
Common 3-state output enable
input
I
CC
category: MSI
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from
40 to +85 and +125
°
C.
DESCRIPTION
The 74AHC/AHCT374 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT374 are octal D-type flip-flops featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus oriented applications.
A clock (CP) and an output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the
set-up and hold times requirements on the LOW-to-HIGH CP transition.
When OE is LOW the contents of the 8 flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation
of the OE input does not affect the state of the flip-flops.
The ‘374’ is functionally identical to the ‘534’, but has non-inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay;
CP to Q
n
maximum clock frequency
input capacitance
output capacitance
power dissipation
capacitance
C
L
= 15 pF; V
CC
= 5 V
3.5
5.0
ns
f
max
C
I
C
O
C
PD
C
L
= 15 pF; V
CC
= 5 V
V
I
= V
CC
or GND
50
3.0
4.0
10
3.0
4.0
12
MHz
pF
pF
pF
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
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