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參數(shù)資料
| 型號： | 7HCPL-5230-200 |
| 英文描述： | Hermetically Sealed, Low IF, Wide VCC, Logic Gate Optocouplers |
| 中文描述： | 密封，中頻，寬虛擬通道連接，低邏輯門光電耦合器 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 294K |
| 代理商： | 7HCPL-5230-200 |
8
Notes:
1. Peak Forward Input Current pulse width < 50
μ
s at 1 KHz maximum repetition rate.
2. Each channel of a multichannel device.
3. Duration of output short circuit time not to exceed 10 ms.
4. All devices are considered two-terminal devices: measured between all input leads or terminals shorted together and all output leads
or terminals shorted together.
5. This is a momentary withstand test, not an operating condition.
6. CM
is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (V
O
< 0.8 V). CM
H
is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic
high state (V
> 2.0 V).
7. t
propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge
of the output pulse. The t
propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V
point on the trailing edge of the output pulse.
8. Measured between each input pair shorted together and all output connections for that channel shorted together.
9. Measured between adjacent input pairs shorted together for each multichannel device.
10. Zero-bias capacitance measured between the LED anode and cathode.
11. Standard parts receive 100% testing at 25
°
C (Subgroups 1 and 9). SMD, Class H and Class K parts receive 100% testing at 25, 125,
and –55
°
C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
12. Parameters are tested as part of device initial characterization and after design and process changes. Parameters guaranteed to limits
specified for all lots not specifically tested.
Single Channel Product Only
Parameter
Output Enable Time to Logic High
Output Enable Time to Logic Low
Output Disable Time from Logic High
Output Disable Time from Logic Low
Symbol
t
PZH
t
PZL
t
PHZ
t
PLZ
Typ.
30
30
45
55
Units
ns
ns
ns
ns
Test Conditions
Fig.
8
8
8
8
Notes
Dual and Quad Channel Products Only
RH = 45%, T
A
= 25
°
C,
V
I-I
= 500 V, t = 5 s
V
I-I
= 500 V
f = 1 MH
Input-Input Insulation Leakage Current
I
I-I
0.5
nA
9
9
9
Resistance (Input-Input)
Capacitance (Input-Input)
R
I-I
C
I-I
10
13
1.5
pF
Typical Characteristics (cont’d.)
All typical values are at T
A
= 25
°
C, V
CC
= 5 V I
F(ON)
= 5 mA, unless otherwise specified.
Figure 1. Typical Logic Low Output
Voltage vs. Temperature.
Figure 2. Typical Logic High Output
Current vs. Temperature.
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