參數(shù)資料
型號: 7LVC646APWDH
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: Octal bus transceiver/register 3-State
中文描述: LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24
文件頁數(shù): 2/16頁
文件大?。?/td> 138K
代理商: 7LVC646APWDH
Philips Semiconductors
Product specification
74LVC646A
Octal bus transceiver/register (3-State)
2
1998 Jul 29
853-2105 19803
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Flow-through pin-out architecture
In accordance with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic
DESCRIPTION
The 74LVC646A is a high performance, low-power, low-voltage
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC646A consist of non-inverting bus transceiver circuits
with 3-State outputs, D-type flip-flops and control circuitry arranged
for multiplexed transmission of data directly from the internal
registers. Data on the ‘A’ or ‘B’ bus will be clocked in the internal
registers, as the appropriate clock (CPAB or CPBA) goes to a HIGH
logic level. Output enable (OE) and direction (DIR) inputs are
provided to control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in either the
‘A’ or ‘B’ register, or in both. The select source inputs (SAB and
SBA) can multiplex stored and real-time (transparent mode) data.
The direction (DIR) input determines which bus will receive data
when OE is active (LOW). In the isolation mode (OE = HIGH), ‘A’
data may be stored in the ‘B’ register and/or ‘B’ data may be stored
in the ‘A’ register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, ‘A’ or ‘B’ may be driven at a time.
The ‘646A’ is functionally identical to the ‘648A’ but has non-inverting
data paths.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
= t
f
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
An to Yn
Maximum clock frequency
Input capacitance
Input/output capacitance
Power dissipation capacitance per gate
C
L
= 50pF
V
CC
= 3.3V
3.9
250
5.0
10
26
ns
f
max
C
I
C
I/O
C
PD
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
V
CC2
x f
i
Σ
(C
L
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
= supply voltage in V;
Σ
(C
V
CC2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
MHz
pF
pF
pF
Notes 1, 2
V
CC2
f
o
) where:
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PKG. DWG. #
24-Pin Plastic SO
–40
°
C to +85
°
C
74LVC646A D
74LVC646A D
SOT137-1
24-Pin Plastic SSOP Type II
–40
°
C to +85
°
C
–40
°
C to +85
°
C
74LVC646A DB
74LVC646A DB
SOT340-1
24-Pin Plastic TSSOP Type I
74LVC646A PW
7LVC646APW DH
SOT355-1
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