參數(shù)資料
型號: 7LVC841APWDH
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: 10-bit transparent latch with 5-volt tolerant inputs/outputs 3-State
中文描述: LVC/LCX/Z SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24
文件頁數(shù): 6/10頁
文件大小: 101K
代理商: 7LVC841APWDH
Philips Semiconductors
Product specification
74LVC841A
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
1998 Jun 17
6
AC WAVEFORMS
V
M
= 1.5 V at V
CC
2.7 V
V
M
= 0.5 V
×
V
CC
at V
CC
<
2.7 V
V
M
= 1.5 V at V
CC
=
3.0 V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
V
X
= V
OL
+
0.3 V at V
CC
2.7 V
V
X
= V
OL
+
0.1
×
V
CC
at V
CC
<
2.7 V
V
Y
= V
OH
– 0.3 V at V
CC
2.7 V
V
Y
= V
OH
– 0.1
×
V
CC
at V
CC
<
2.7 V
SV01727
D
n
Input
Q
n
Output
t
PLH
t
PHL
V
M
V
M
V
I
GND
V
OL
V
OH
Figure 1. Input (D
n
) to output (Q
n
) propagation delays.
SV01729
VM
LE INPUT
VI
GND
VOL
VOH
Qn OUTPUT
VM
tPLH
tPHL
tW
Figure 2. Latch enable input (LE) pulse width, the latch enable
input to output (Q
n
) propagation delays.
SV01728
outputs
disabled
outputs
enabled
outputs
enabled
t
PHZ
t
PZH
t
PZL
t
PLZ
V
X
V
Y
V
M
V
M
V
M
OE INPUT
Q
OUTPUT
LOW-to-OFF
OFF-to-LOW
Q
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
V
OL
GND
GND
V
OH
V
CC
V
I
Figure 3. 3-State enable and disable times.
SV01730
VM
Dn INPUT
LE INPUT
GND
VI
VI
GND
VM
tsu
tsu
th
th
Figure 4. Data set-up and hold times for the
D
n
input to LE input.
Note to Figure 4:
The shaded areas indicate when the input is
permitted to change for predictable output performance
TEST CIRCUIT
PULSE
GENERATOR
V
I
R
T
D.U.T.
V
O
C
L
50pF
S
1
2 x V
CC
Open
GND
500
500
V
CC
V
I
2.7V
V
CC
2.7V
2.7V – 3.6V
Test
S
1
GND
t
PLZ
/t
PZL
t
PHZ
/t
PZH
2 x V
CC
t
PLH
/t
PHL
Open
SY00003
V
CC
Figure 5. Load circuitry for switching times.
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